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| this is information on a product in full production. february 2014 docid025451 rev 2 1/123 stm32f071xx arm-based 32-bit mcu, up to 128 kb flash, 12 timers, adc, dac & communication interfaces, 2.0 - 3.6 v datasheet - production data features ? core: arm ? 32-bit cortex ? -m0 cpu, frequency up to 48 mhz ? memories ? 64 to 128 kbytes of flash memory ? 16 kbytes of sram with hw parity ? crc calculation unit ? reset and power management ? digital & i/os supply: v dd = 2.0 v to 3.6 v ? analog supply: v dda = v dd to 3.6 v ? selected i/os: v ddio2 = 1.65 v to 3.6 v ? power-on/power down reset (por/pdr) ? programmable voltage detector (pvd) ? low power modes: sleep, stop, standby ?v bat supply for rtc and backup registers ? clock management ? 4 to 32 mhz crystal oscillator ? 32 khz oscillator for rtc with calibration ? internal 8 mhz rc with x6 pll option ? internal 40 khz rc oscillator ? internal 48 mhz oscillator with automatic trimming based on ext. synchronization ? up to 87 fast i/os ? all mappable on external interrupt vectors ? up to 68 i/os with 5v tolerant capability and 19 with independent supply v ddio2 ? 7-channel dma controller ? one 12-bit, 1.0 s adc (up to 16 channels) ? conversion range: 0 to 3.6 v ? separate analog supply: 2.4 v to 3.6 v ? one 12-bit d/a converter (with 2 channels) ? two fast low-power analog comparators with programmable input and output ? up to 24 capacitive sensing channels for touchkey, linear and rotary touch sensors ? calendar rtc with alarm and periodic wakeup from stop/standby ? 12 timers ? one 16-bit advanced-control timer for 6 channel pwm output ? one 32-bit and seven 16-bit timers, with up to 4 ic/oc, ocn, usable for ir control decoding or dac control ? independent and system watchdog timers ? systick timer ? communication interfaces ? two i 2 c interfaces supporting fast mode plus (1 mbit/s) with 20 ma current sink; one supporting smbus/pmbus and wakeup ? four usarts supporting master synchronous spi and modem control; two with iso7816 interface, lin, irda, auto baud rate detection and wakeup feature ? two spis (18 mbit/s) with 4 to 16 programmable bit frames, and with i 2 s interface multiplexed ? hdmi cec, wakeup on header reception ? serial wire debug (swd) ? 96-bit unique id ? all packages ecopack ? 2 table 1. device summary reference part number stm32f071xb stm32f071cb, stm32f071rb, stm32f071vb stm32f071x8 stm32f071v8 lqfp100 14x14 mm lqfp64 10x10 mm lqfp48 7x7 mm ufqfpn48 7x7 mm wlcsp49 0.4 mm pitch ufbga100 7x7 mm www.st.com
contents stm32f071xx 2/123 docid025451 rev 2 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 arm cortex-m0 core with embedded flash and sram . . . . . . . . . . . . . 13 3.2 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 cyclic redundancy check calculation unit (crc) . . . . . . . . . . . . . . . . . . . 14 3.5 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5.2 power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.7 general-purpose inputs/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.8 direct memory access controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.9 interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.9.1 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 18 3.9.2 extended interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . 18 3.10 analog to digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.10.1 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.10.2 internal voltage reference (v refint ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.10.3 v bat battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.11 digital-to-analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12 comparators (comp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.13 touch sensing controller (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.14 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.14.1 advanced-control timer (tim1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.14.2 general-purpose timers (tim2..3, tim14..17) . . . . . . . . . . . . . . . . . . . . 23 3.14.3 basic timers tim6 and tim7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.14.4 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.14.5 system window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 docid025451 rev 2 3/123 stm32f071xx contents 4 3.14.6 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.15 real-time clock (rtc) and backup registers . . . . . . . . . . . . . . . . . . . . . . 24 3.16 inter-integrated circuit interfaces (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.17 universal synchronous/asynchronous receiver transmitters (usart) . . 26 3.18 serial peripheral interface (spi)/inter-integrated sound interfaces (i 2 s) . 27 3.19 high-definition multimedia interface (hdmi) - consumer electronics control (cec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.20 clock recovery system (crs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.21 serial wire debug port (sw-dp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4 pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3.2 operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 52 6.3.3 embedded reset and power control block characteristics . . . . . . . . . . . 52 6.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3.6 wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.3.7 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.3.8 internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.9 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.10 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 contents stm32f071xx 4/123 docid025451 rev 2 6.3.12 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.13 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.14 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3.15 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.16 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3.17 dac electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.18 comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3.19 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.20 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.21 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3.22 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 7.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 7.2.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 118 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 docid025451 rev 2 5/123 stm32f071xx list of tables 6 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f071xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 4. internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. capacitive sensing gpios available on stm32f071xx devices . . . . . . . . . . . . . . . . . . . . 21 table 6. no. of capacitive sensing channels available on stm32f071xx devices. . . . . . . . . . . . . . 21 table 7. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 9. stm32f071xx i 2 c implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 10. stm32f071xx usart implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 11. stm32f071xx spi/i2s implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 12. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 13. stm32f071xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 14. alternate functions selected through gpioa_afr registers for port a . . . . . . . . . . . . . . . 40 table 15. alternate functions selected through gpiob_afr registers for port b . . . . . . . . . . . . . . . 41 table 16. alternate functions selected through gpioc_afr registers for port c . . . . . . . . . . . . . . . 42 table 17. alternate functions selected through gpiod_afr registers for port d . . . . . . . . . . . . . . . 42 table 18. alternate functions selected through gpioe_afr registers for port e . . . . . . . . . . . . . . . 43 table 19. alternate functions available on port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 20. stm32f071xx peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 21. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 22. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 23. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 24. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 25. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 26. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 27. programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 28. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 29. typical and maximum current consumption from v dd supply at v dd = 3.6 v . . . . . . . . . . 54 table 30. typical and maximum current consumption from the v dda supply . . . . . . . . . . . . . . . . . . 56 table 31. typical and maximum consumption in stop and standby modes . . . . . . . . . . . . . . . . . . . 57 table 32. typical and maximum current consumption from the v bat supply. . . . . . . . . . . . . . . . . . . 58 table 33. typical current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 table 34. typical current consumption in sleep mode, code running from flash . . . . . . . . . . . . . . . 60 table 35. switching output i/o current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 36. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 table 37. low-power mode wakeup timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 38. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 39. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 40. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 41. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 42. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 43. hsi14 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 44. hsi48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 45. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 46. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 47. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 list of tables stm32f071xx 6/123 docid025451 rev 2 table 48. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 49. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 50. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 51. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 52. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 53. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 54. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 55. output voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 56. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 57. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 58. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 59. r ain max for f adc = 14 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 60. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 61. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 62. comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 63. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 64. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 65. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 66. iwdg min/max timeout period at 40 khz (lsi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 67. wwdg min/max timeout value at 48 mhz (pclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 68. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 69. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 70. i 2 s characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 table 71. ufbga100 ? ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 72. ufbga100 recommended pcb design rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 73. lqfp100 ? 14 x 14 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . 103 table 74. lqfp64 ? 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . 106 table 75. lqfp48 ? 7 x 7 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . 109 table 76. ufqfpn48 ? 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . 113 table 77. wlcsp49 ? 0.4 mm pitch package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 78. wlcsp49 recommended pcb design rules (0.4 mm pitch bga) . . . . . . . . . . . . . . . . . . 117 table 79. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 80. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 81. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 docid025451 rev 2 7/123 stm32f071xx list of figures 8 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 3. ufbga100 package ballout (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 4. lqfp100 100-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 5. lqfp64 64-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 6. lqfp48 48-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 7. ufqfpn48 48-pin package pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 8. wlcsp49 49-pin package ballout (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 9. stm32f071xx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 figure 10. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 11. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 12. power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 13. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 14. high-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 15. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 16. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 figure 17. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 18. hsi oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 19. hsi14 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 20. hsi48 oscillator accuracy characterization results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 21. tc and tta i/o input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 figure 22. five volt tolerant (ft and ftf) i/o input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 23. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 24. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 25. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 26. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 27. 12-bit buffered / non-buffered dac. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 figure 28. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 29. spi timing diagram - slave mode and cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 30. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 31. i2s slave timing diagram (philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 figure 32. i2s master timing diagram (philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 33. ufbga100 ? ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 34. ufbga100 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 35. ufbga100 package top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 02 figure 36. lqfp100 ? 14 x 14 mm 100 pin low-profile quad flat package outline. . . . . . . . . . . . . . . 103 figure 37. lqfp100 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 38. lqfp100 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 39. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline. . . . . . . . . . . . . . . . . 106 figure 40. lqfp64 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 figure 41. lqfp64 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 42. lqfp48 ? 7 x 7 mm, 48 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 109 figure 43. lqfp48 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 0 figure 44. lqfp48 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 45. ufqfpn48 ? 7 x 7 mm, 0.5 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 46. ufqfpn48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 47. ufqfpn48 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 list of figures stm32f071xx 8/123 docid025451 rev 2 figure 48. wlcsp49 ? 0.4 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 49. wlcsp49 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 50. wlcsp49 package top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 17 figure 51. lqfp64 p d max vs. t a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 docid025451 rev 2 9/123 stm32f071xx introduction 28 1 introduction this datasheet provides the ordering information and mechanical device characteristics of the stm32f071xx microcontrollers. this document should be read in conjunction with the stm32f0xxxx reference manual (rm0091). the reference manual is available from the stmicroelectronics website www.st.com. for information on the arm ? cortex ? -m0 core, please refer to the cortex ? -m0 technical reference manual, available from the www.arm.com website. description stm32f071xx 10/123 docid025451 rev 2 2 description the stm32f071xx microcontrollers incorporate the high-performance arm ? cortex ? -m0 32-bit risc core operating at a 48 mhz frequency, high-speed embedded memories (up to 128 kbytes of flash memory and 16 kbytes of sram), and an extensive range of enhanced peripherals and i/os. all devices offer standard communication interfaces (two i 2 cs, two spis/one i2s, one hdmi cec and four usarts), one 12-bit adc, one 12-bit dac with two channels, seven general-purpose 16-bit timers, a 32-bit timer and an advanced-control pwm timer. the stm32f071xx microcontrollers operate in the -40 to +85 c and -40 to +105 c temperature ranges from a 2.0 to 3.6 v power supply. a comprehensive set of power-saving modes allows the design of low-power applications. the stm32f071xx microcontrollers include devices in six different packages ranging from 48 pins to 100 pins with a die form also available upon request. depending on the device chosen, different sets of peripherals are included. the description below provides an overview of the complete range of stm32f071xx peripherals proposed. these features make the stm32f071xx microcontrollers suitable for a wide range of applications such as application control and user interfaces, handheld equipment, a/v receivers and digital tv, pc peripherals, gaming and gps platforms, industrial applications, plcs, inverters, printers, scanners, alarm systems, video intercoms, and hvacs. docid025451 rev 2 11/123 stm32f071xx description 28 table 2. stm32f071xx family device features and peripheral counts peripheral stm32f071cb stm32f071rb stm32f071vx flash (kbytes) 128 128 64 128 sram (kbytes) 16 16 16 timers advanced control 1 (16-bit) general purpose 5 (16-bit) 1 (32-bit) basic 2 (16-bit) comm. interfaces spi [i2s] (1) 2 [2] i 2 c2 usart 4 cec 1 12-bit adc (number of channels) 1 (10 ext. + 3 int.) 1 (16 ext. + 3 int.) gpios 37 51 87 capacitive sensing channels 17 18 24 12-bit dac (number of channels) 1 (2) analog comparator 2 max. cpu frequency 48 mhz operating voltage 2.0 to 3.6 v operating temperature ambient operating temperature: -40 c to 85 c / -40 c to 105 c junction temperature: -40 c to 125 c packages lqfp48 ufqfpn48 wlcsp49 lqfp64 lqfp100 ufbga100 1. the spi interface can be used either in spi mode or in i2s audio mode. description stm32f071xx 12/123 docid025451 rev 2 figure 1. block diagram 0 6 y 9 f k d q q h o v f r p s o f k d q q h o v % 5 . ( 7 5 l q s x w d v $ ) f k ( 7 5 d v $ ) f k ( 7 5 d v $ ) f k d q q h o d v $ ) f k d q q h o v f r p s o % 5 . d v $ ) f k d q q h o f r p s o % 5 . d v $ ) f k d q q h o f r p s o % 5 . d v $ ) , 5 b 2 8 7 d v $ ) 5 ; 7 ; & 7 6 5 7 6 & . d v $ ) 5 ; 7 ; & 7 6 5 7 6 & . d v $ ) 6 & / 6 ' $ 6 0 % $ p $ i r u ) 0 d v $ ) 6 & / 6 ' $ p $ i r u ) 0 d v $ ) & ( & d v $ ) ' $ & b 2 8 7 # 9 ' ' , 2 # 9 ' ' $ # 9 ' ' $ $ + % 3 & / . $ 3 % 3 & / . $ ' & & / . 8 6 $ 5 7 & / . + & / . ) & / . & ( & & / . 3 $ > @ 3 % > @ 3 & > @ 3 ' > @ 3 ) > @ 3 ) 3 ) > @ j u r x s v r i f k d q q h o v 6 < 1 & # 9 ' ' $ $ ) 0 2 6 , 6 ' 0 , 6 2 0 & . 6 & . & . 1 6 6 : 6 d v $ ) # 9 ' ' $ 9 ' ' $ 9 6 6 $ * 3 ' 0 $ f k d q q h o v & 2 5 7 ( ; 0 & 3 8 i 0 $ ; 0 + ] 6 h u l d o : l u h ' h e x j 1 9 , & * 3 , 2 s r u w $ * 3 , 2 s r u w % * 3 , 2 s r u w & * 3 , 2 s r u w ( * 3 , 2 s r u w ) 7 r x f k 6 h q v l q j & r q w u r o o h u 3 $ ' $ q d o r j v z l w f k h v ( ; 7 , 7 : . 8 3 6 3 , , 6 6 3 , , 6 6 < 6 & ) * , ) * 3 f r p s d u d w r u 7 , 0 ( 5 ' % * 0 & 8 : , q g r z : ' * $ 3 % $ + % & 5 & 5 ( 6 ( 7 & / 2 & . & 2 1 7 5 2 / 3 : 0 7 , 0 ( 5 7 , 0 ( 5 e l w 7 , 0 ( 5 7 , 0 ( 5 7 , 0 ( 5 7 , 0 ( 5 7 , 0 ( 5 8 6 $ 5 7 8 6 $ 5 7 , & , & + ' 0 , & ( & , ) e l w ' $ & 3 r z h u & r q w u r o o h u ; 7 $ / 2 6 & 0 + ] , q g : l q g r z : ' * 6 8 3 3 / < 6 8 3 ( 5 9 , 6 , 2 1 3 9 ' 3 2 5 3 ' 5 3 2 : ( 5 9 2 / 7 5 ( * 9 7 2 9 5 & + 6 0 + ] 5 & + 6 0 + ] 5 & / 6 3 / / ) o d v k l q w h u i d f h ) o d v k * 3 / 8 s w r . % e l w v 2 e o 6 5 $ 0 . % 6 5 $ 0 f r q w u r o o h u 7 h p s v h q v r u , ) e l w $ ' & 6 : & / . 6 : ' , 2 d v $ ) , 1 3 8 7 , 1 3 8 7 2 8 7 3 8 7 d v $ ) $ ' l q s x w v * 3 f r p s d u d w r u $ + % g h f r g h u % x v p d w u l [ # 9 ' ' $ # 9 ' ' , 2 9 ' ' 3 2 5 5 h v h w , q w 9 ' ' , 2 w r 9 9 6 6 1 5 6 7 9 ' ' $ 9 6 6 $ 2 6 & b , 1 3 ) 2 6 & b 2 8 7 3 ) 9 % $ 7 w r 9 2 6 & b , 1 2 6 & b 2 8 7 7 $ 0 3 ( 5 5 7 & $ / $ 5 0 2 8 7 5 7 & % d f n x s u h j 5 7 & l q w h u i d f h ; 7 $ / n + ] # 9 6 : 5 ; 7 ; & 7 6 5 7 6 & . d v $ ) 5 ; 7 ; & 7 6 5 7 6 & . d v $ ) 8 6 $ 5 7 8 6 $ 5 7 e l w ' $ & 7 , 0 ( 5 ' $ & b 2 8 7 * 3 , 2 s r u w ' 3 ( > @ 5 & + 6 0 + ] 9 ' ' 8 6 % 2 . , 1 & 5 6 6 < 1 & 0 2 6 , 6 ' 0 , 6 2 0 & . 6 & . & . 1 6 6 : 6 d v $ ) docid025451 rev 2 13/123 stm32f071xx functional overview 28 3 functional overview 3.1 arm cortex-m0 core with embedded flash and sram the arm cortex-m0 processor is the latest generation of arm processors for embedded systems. it has been developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. the arm cortex-m0 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the stm32f0xx family has an embedded arm core and is therefore compatible with all arm tools and software. figure 1 shows the general block diagram of the device family. 3.2 memories the device has the following features: ? 16 kbytes of embedded sram accessed (read/write) at cpu clock speed with 0 wait states and featuring embedded parity checking with exception generation for fail-critical applications. ? the non-volatile memory is divided into two arrays: ? 64 to 128 kbytes of embedded flash memory for programs and data ? option bytes the option bytes are used to write-protect the memory (with 4 kb granularity) and/or readout-protect the whole memory with the following options: ? level 0: no readout protection ? level 1: memory readout protection, the flash memory cannot be read from or written to if either debug features are connected or boot in ram is selected ? level 2: chip readout protection, debug features (cortex-m0 serial wire) and boot in ram selection disabled 3.3 boot modes at startup, the boot pin and boot selector option bits are used to select one of the three boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart on pins pa14/pa15 or pa9/pa10, i2c on pins pb6/pb7. functional overview stm32f071xx 14/123 docid025451 rev 2 3.4 cyclic redundancy check calculation unit (crc) the crc (cyclic redundancy check) calculation unit is used to get a crc code using a configurable generator polynomial value and size. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. 3.5 power management 3.5.1 power supply schemes ? v dd = 2.0 to 3.6 v: external power supply for i/os and the internal regulator. provided externally through v dd pins. ? v dda = 2.0 to 3.6 v: external analog power supply for adc, reset blocks, rcs and pll (minimum voltage to be applied to v dda is 2.4 v when the adc is used). the v dda voltage level must be always greater or equal to the v dd voltage level and must be provided first. ? v ddio2 = 1.65 to 3.6 v: external power supply for marked i/os. provided externally through the vddio2 pin. the v ddio2 voltage level is completely independent from v dd or v dda , but it must not be provided without a valid supply on v dd . refer to the pinout diagrams or tables for concerned i/os list. ? v bat = 1.65 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. 3.5.2 power supply supervisors the device has integrated power-on reset (por) and power-down reset (pdr) circuits. they are always active, and ensure proper operation above a threshold of 2 v. the device remains in reset mode when the monitored supply voltage is below a specified threshold, v por/pdr , without the need for an external reset circuit. ? the por monitors only the v dd supply voltage. during the startup phase it is required that v dda should arrive first and be greater than or equal to v dd . ? the pdr monitors both the v dd and v dda supply voltages, however the v dda power supply supervisor can be disabled (by programming a dedicated option bit) to reduce the power consumption if the application design ensures that v dda is higher than or equal to v dd . the v ddio2 supply is monitored and compared with the internal reference voltage (v refint ). when the v ddio2 is below this threshold, all the i/os supplied from this rail are disabled by hardware. the output of this comparator is connected to exti line 31 and it can be used to generate an interrupt. the device features an embedded programmable voltage detector (pvd) that monitors the v dd power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd drops below the v pvd threshold and/or when v dd is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. docid025451 rev 2 15/123 stm32f071xx functional overview 28 3.5.3 voltage regulator the regulator has two operating modes and it is always enabled after reset. ? main (mr) is used in normal operating mode (run). ? low power (lpr) can be used in stop mode where the power demand is reduced. in standby mode, it is put in power down mode. in this mode, the regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and sram are lost). 3.5.4 low-power modes the stm32f071xx microcontrollers support three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode stop mode achieves very low power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled. the voltage regulator can also be put either in normal or in low power mode. the device can be woken up from stop mode by any of the exti lines. the exti line source can be one of the 16 external lines, the pvd output, rtc alarm, i2c1, usart1 or the cec. the i2c1, usart1 and the cec can be configured to enable the hsi rc oscillator for processing incoming data. if this is used when the voltage regulator is put in low power mode, the regulator is first switched to normal mode before the clock is provided to the given peripheral. ? standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.8 v domain is powered off. the pll, the hsi rc and the hse crystal oscillators are also switched off. after entering standby mode, sram and register contents are lost except for registers in the rtc domain and standby circuitry. the device exits standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pins, or an rtc event occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering stop or standby mode. functional overview stm32f071xx 16/123 docid025451 rev 2 3.6 clocks and startup system clock selection is performed on startup, however the internal rc 8 mhz oscillator is selected as default cpu clock on reset. an external 4-32 mhz clock can be selected, in which case it is monitored for failure. if failure is detected, the system automatically switches back to the internal rc oscillator. a software interrupt is generated if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). several prescalers allow the application to configure the frequency of the ahb and the apb domains. the maximum frequency of the ahb and the apb domains is 48 mhz. additionally, also the internal rc 48 mhz oscillator can be selected for system clock or pll input source. this oscillator can be automatically fine-trimmed by the means of the crs peripheral using the external synchronization. docid025451 rev 2 17/123 stm32f071xx functional overview 28 figure 2. clock tree 3.7 general-purpose inputs/outputs (gpios) each of the gpio pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. the i/o configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. 0 + ] + 6 ( 2 6 & 2 6 & b , 1 2 6 & b 2 8 7 2 6 & b , 1 2 6 & b 2 8 7 0 + ] + 6 , 5 & w r , : ' * 3 / / [ [ [ 3 / / 0 8 / 0 & 2 0 d l q f o r f n r x w s x w $ + % 3 / / & / . + 6 , + 6 ( $ 3 % s u h v f d o h u + & / . 3 / / & / . w r $ + % e x v f r u h p h p r u \ d q g ' 0 $ w r $ ' & f o r f n l q s x w / 6 ( / 6 , + 6 , + 6 , + 6 ( w r 5 7 & 3 / / 6 5 & 6 : 0 & 2 6 < 6 & / . 5 7 & & / . 5 7 & 6 ( / > @ 6 < 6 & / . w r 7 , 0 , i $ 3 % s u h v f d o h u [ h o v h [ ) / , 7 ) & / . w r ) o d v k + 6 , 0 + ] + 6 , 5 & + 6 , / 6 ( w r , & w r 8 6 $ 5 7 w r 8 6 $ 5 7 / 6 ( + 6 , 6 < 6 & / . 3 & / . 6 < 6 & / . + 6 , 3 & / . 0 6 9 w r , 6 w r & ( & w r f r u w h [ 6 \ v w h p w l p h u ) + & / . & r u w h [ i u h h u x q q l q j f o r f n w r $ 3 % s h u l s k h u d o v $ + % s u h v f d o h u & 6 6 / 6 ( 2 6 & n + ] / 6 , 5 & n + ] / 6 , / 6 ( & 5 6 0 + ] + 6 , 5 & + 6 , 3 5 ( ' , 9 + 6 , 3 / / 1 2 ' , 9 s u r j u d p p l q j l q w h u i d f h 0 & 2 3 5 ( w r 7 , 0 d v \ q f k u r q r x v functional overview stm32f071xx 18/123 docid025451 rev 2 3.8 direct memory access controller (dma) the 7-channel general-purpose dmas manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. the dma supports circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. each channel is connected to dedicated hardware dma requests, with support for software trigger on each channel. configuration is made by software and transfer sizes between source and destination are independent. dma can be used with the main peripherals: spi, i2s, i2c, usart, all timx timers (except tim14), dac and adc. 3.9 interrupts and events 3.9.1 nested vectored interrupt controller (nvic) the stm32f0xx family embeds a nested vectored interrupt controller able to handle up to 32 maskable interrupt channels (not including the 16 interrupt lines of cortex-m0) and 4 priority levels. ? closely coupled nvic gives low latency interrupt processing ? interrupt entry vector table address passed directly to the core ? closely coupled nvic core interface ? allows early processing of interrupts ? processing of late arriving higher priority interrupts ? support for tail-chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimal interrupt latency. 3.9.2 extended interrupt/event controller (exti) the extended interrupt/event controller consists of 32 edge detector lines used to generate interrupt/event requests and wake-up the system. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal clock period. up to 87 gpios can be connected to the 16 external interrupt lines. 3.10 analog to digital converter (adc) the 12-bit analog to digital converter has up to 16 external and 3 internal (temperature sensor, voltage reference, vbat voltage measurement) channels and performs conversions in single-shot or scan modes. in scan mode, automatic conversion is performed on a selected group of analog inputs. the adc can be served by the dma controller. docid025451 rev 2 19/123 stm32f071xx functional overview 28 an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. 3.10.1 temperature sensor the temperature sensor (ts) generates a voltage v sense that varies linearly with temperature. the temperature sensor is internally connected to the adc_in16 input channel which is used to convert the sensor output voltage into a digital value. the sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. as the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. to improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by st. the temperature sensor factory calibration data are stored by st in the system memory area, accessible in read-only mode. 3.10.2 internal voltage reference (v refint ) the internal voltage reference (v refint ) provides a stable (bandgap) voltage output for the adc. v refint is internally connected to the adc_in17 input channel. the precise voltage of v refint is individually measured for each part by st during production test and stored in the system memory area. it is accessible in read-only mode. 3.10.3 v bat battery voltage monitoring this embedded hardware feature allows the application to measure the v bat battery voltage using the internal adc channel adc_in18. as the v bat voltage may be higher than v dda , and thus outside the adc input range, the v bat pin is internally connected to a bridge divider by 2. as a consequence, the converted digital value is half the v bat voltage. table 3. temperature sensor calibration values calibration value name description memory address ts_cal1 ts adc raw data acquired at a temperature of 30 c ( ?? 5 c), v dda = 3.3 v ( ?? 10 mv) 0x1fff f7b8 - 0x1fff f7b9 ts_cal2 ts adc raw data acquired at a temperature of 110 c ( ?? 5 c), v dda = 3.3 v ( ?? 10 mv) 0x1fff f7c2 - 0x1fff f7c3 table 4. internal voltage reference calibration values calibration value name description memory address vrefint_cal raw data acquired at a temperature of 30 c ( ?? 5 c), v dda = 3.3 v ( ?? 10 mv) 0x1fff f7ba - 0x1fff f7bb functional overview stm32f071xx 20/123 docid025451 rev 2 3.11 digital-to-analog converter (dac) the two 12-bit buffered dac channels can be used to convert digital signals into analog voltage signal outputs. the chosen design structure is composed of integrated resistor strings and an amplifier in non-inverting configuration. this digital interface supports the following features: ? 8-bit or 12-bit monotonic output ? left or right data alignment in 12-bit mode ? synchronized update capability ? noise-wave generation ? triangular-wave generation ? dual dac channel independent or simultaneous conversions ? dma capability for each channel ? external triggers for conversion six dac trigger inputs are used in the device. the dac is triggered through the timer trigger outputs and the dac interface is generating its own dma requests. 3.12 comparators (comp) the device embeds two fast rail-to-rail low-power comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low power) and with selectable output polarity. the reference voltage can be one of the following: ? external i/o ? dac output pins ? internal reference voltage or submultiple (1/4, 1/2, 3/4). refer to table 28: embedded internal reference voltage for the value and precision of the internal reference voltage. both comparators can wake up from stop mode, generate interrupts and breaks for the timers and can be also combined into a window comparator. 3.13 touch sensing controller (tsc) the stm32f071xx devices provide a simple solution for adding capacitive sensing functionality to any application. these devices offer up to 24 capacitive sensing channels distributed over 8 analog i/o groups. capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic...). the capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. it consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. to limit the cpu bandwidth usage, this acquisition is directly managed by the hardware touch sensing controller and only requires few external components to operate. docid025451 rev 2 21/123 stm32f071xx functional overview 28 the touch sensing controller is fully supported by the stmtouch touch sensing firmware library, which is free to use and allows touch sensing functionality to be implemented reliably in the end application. table 5. capacitive sensing gpios available on stm32f071xx devices group capacitive sensing signal name pin name group capacitive sensing signal name pin name 1 tsc_g1_io1 pa0 5 tsc_g5_io1 pb3 tsc_g1_io2 pa1 tsc_g5_io2 pb4 tsc_g1_io3 pa2 tsc_g5_io3 pb6 tsc_g1_io4 pa3 tsc_g5_io4 pb7 2 tsc_g2_io1 pa4 6 tsc_g6_io1 pb11 tsc_g2_io2 pa5 tsc_g6_io2 pb12 tsc_g2_io3 pa6 tsc_g6_io3 pb13 tsc_g2_io4 pa7 tsc_g6_io4 pb14 3 tsc_g3_io1 pc5 7 tsc_g7_io1 pe2 tsc_g3_io2 pb0 tsc_g7_io2 pe3 tsc_g3_io3 pb1 tsc_g7_io3 pe4 tsc_g3_io4 pb2 tsc_g7_io4 pe5 4 tsc_g4_io1 pa9 8 tsc_g8_io1 pd12 tsc_g4_io2 pa10 tsc_g8_io2 pd13 tsc_g4_io3 pa11 tsc_g8_io3 pd14 tsc_g4_io4 pa12 tsc_g8_io4 pd15 table 6. no. of capacitive sensing channels available on stm32f071xx devices analog i/o group number of capacitive sensing channels stm32f071vx stm32f071rx stm32f071cx g1 3 3 3 g2 3 3 3 g3 3 3 2 g4 3 3 3 g5 3 3 3 g6 3 3 3 g7 3 0 0 g8 3 0 0 number of capacitive sensing channels 24 18 17 functional overview stm32f071xx 22/123 docid025451 rev 2 3.14 timers and watchdogs the stm32f071xx devices include up to six general-purpose timers, two basic timers and an advanced control timer. table 7 compares the features of the advanced-control, general-purpose and basic timers. table 7. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/compare channels complementary outputs advanced control tim1 16-bit up, down, up/down any integer between 1 and 65536 yes 4 yes general purpose tim2 32-bit up, down, up/down any integer between 1 and 65536 yes 4 no tim3 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no tim14 16-bit up any integer between 1 and 65536 no 1 no tim15 16-bit up any integer between 1 and 65536 yes 2 yes tim16, tim17 16-bit up any integer between 1 and 65536 yes 1 yes basic tim6, tim7 16-bit up any integer between 1 and 65536 yes 0 no docid025451 rev 2 23/123 stm32f071xx functional overview 28 3.14.1 advanced-control timer (tim1) the advanced-control timer (tim1) can be seen as a three-phase pwm multiplexed on six channels. it has complementary pwm outputs with programmable inserted dead times. it can also be seen as a complete general-purpose timer. the four independent channels can be used for: ? input capture ? output compare ? pwm generation (edge or center-aligned modes) ? one-pulse mode output if configured as a standard 16-bit timer, it has the same features as the timx timer. if configured as the 16-bit pwm generator, it has full modulation capability (0-100%). the counter can be frozen in debug mode. many features are shared with those of the standard timers which have the same architecture. the advanced control timer can therefore work together with the other timers via the timer link feature for synchronization or event chaining. 3.14.2 general-purpose timers (tim2..3, tim14..17) there are six synchronizable general-purpose timers embedded in the stm32f071xx devices (see table 7 for differences). each general-purpose timer can be used to generate pwm outputs, or as simple time base. tim2, tim3 stm32f071xx devices feature two synchronizable 4-channel general-purpose timers. tim2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. tim3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. they feature 4 independent channels each for input capture/output compare, pwm or one-pulse mode output. this gives up to 12 input captures/output compares/pwms on the largest packages. the tim2 and tim3 general-purpose timers can work together or with the tim1 advanced- control timer via the timer link feature for synchronization or event chaining. tim2 and tim3 both have independent dma request generation. these timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. their counters can be frozen in debug mode. tim14 this timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim14 features one single channel for input capture/output compare, pwm or one-pulse mode output. its counter can be frozen in debug mode. tim15, tim16 and tim17 these timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. tim15 has two independent channels, whereas tim16 and tim17 feature one single functional overview stm32f071xx 24/123 docid025451 rev 2 channel for input capture/output compare, pwm or one-pulse mode output. the tim15, tim16 and tim17 timers can work together, and tim15 can also operate withtim1 via the timer link feature for synchronization or event chaining. tim15 can be synchronized with tim16 and tim17. tim15, tim16 and tim17 have a complementary output with dead-time generation and independent dma request generation. their counters can be frozen in debug mode. 3.14.3 basic timers tim6 and tim7 these timers are mainly used for dac trigger generation. they can also be used as a generic 16-bit time base. 3.14.4 independent watchdog (iwdg) the independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and standby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. 3.14.5 system window watchdog (wwdg) the system window watchdog is based on a 7-bit downcounter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the apb clock (pclk). it has an early warning interrupt capability and the counter can be frozen in debug mode. 3.14.6 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: ? a 24-bit down counter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0 ? programmable clock source (hclk or hclk/8) 3.15 real-time clock (rtc) and backup registers the rtc and the 5 backup registers are supplied through a switch that takes power either on v dd supply when present or through the v bat pin. the backup registers are five 32-bit registers used to store 20 bytes of user application data when v dd power is not present. they are not reset by a system or power reset, or when the device wakes up from standby mode. docid025451 rev 2 25/123 stm32f071xx functional overview 28 the rtc is an independent bcd timer/counter. its main features are the following: ? calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format. ? automatically correction for 28, 29 (leap year), 30, and 31 day of the month. ? programmable alarm with wake up from stop and standby mode capability. ? periodic wakeup unit with programmable resolution and period. ? on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize it with a master clock. ? digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy. ? 3 anti-tamper detection pins with programmable filter. the mcu can be woken up from stop and standby modes on tamper event detection. ? timestamp feature which can be used to save the calendar content. this function can triggered by an event on the timestamp pin, or by a tamper event. the mcu can be woken up from stop and standby modes on timestamp event detection. ? reference clock detection: a more precise second source clock (50 or 60 hz) can be used to enhance the calendar precision. the rtc clock sources can be: ? a 32.768 khz external crystal ? a resonator or oscillator ? the internal low-power rc oscillator (typical frequency of 40 khz) ? the high-speed external clock divided by 32 3.16 inter-integrated circuit interfaces (i 2 c) up to two i 2 c interfaces (i2c1 and i2c2) can operate in multimaster or slave modes. both can support standard mode (up to 100 kbit/s), fast mode (up to 400 kbit/s) and fast mode plus (up to 1 mbit/s) with 20 ma output drive on some i/os. both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). they also include programmable analog and digital noise filters. in addition, i2c1 provides hardware support for smbus 2.0 and pmbus 1.1: arp capability, host notify protocol, hardware crc (pec) generation/verification, timeouts table 8. comparison of i2c analog and digital filters analog filter digital filter pulse width of suppressed spikes ? 50 ns programmable length from 1 to 15 i2c peripheral clocks benefits available in stop mode 1. extra filtering capability vs. standard requirements. 2. stable length drawbacks variations depending on temperature, voltage, process wakeup from stop on address match is not available when digital filter is enabled. functional overview stm32f071xx 26/123 docid025451 rev 2 verifications and alert protocol management. i2c1 also has a clock domain independent from the cpu clock, allowing the i2c1 to wake up the mcu from stop mode on address match. the i2c interfaces can be served by the dma controller. refer to table 9 for the differences between i2c1 and i2c2. 3.17 universal synchronous/asynchronous receiver transmitters (usart) the device embeds up to four universal synchronous/asynchronous receiver transmitters (usart1, usart2, usart3 and usart4), which communicate at speeds of up to 6 mbit/s. they provide hardware management of the cts, rts and rs485 de signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. usart1 and usart2 support also smartcard communication (iso 7816), irda sir endec, lin master/slave capability and auto baud rate feature, and have a clock domain independent from the cpu clock, allowing usart1 and usart2 to wake up the mcu from stop mode. the usart interfaces can be served by the dma controller. refer to table 10 for the differences between usart1, usart2, usart3 and usart4. table 9. stm32f071xx i 2 c implementation i2c features (1) 1. x = supported. i2c1 i2c2 7-bit addressing mode xx 10-bit addressing mode xx standard mode (up to 100 kbit/s) xx fast mode (up to 400 kbit/s) xx fast mode plus with 20ma output drive i/os (up to 1 mbit/s) xx independent clock x smbus x wakeup from stop x table 10. stm32f071xx usart implementation usart modes/features (1) usart1 and usart2 usart3 and usart4 hardware flow control for modem x x continuous communication using dma x x multiprocessor communication x x synchronous mode x x docid025451 rev 2 27/123 stm32f071xx functional overview 28 3.18 serial peripheral interface (spi)/inter-integrated sound interfaces (i 2 s) up to two spis are able to communicate up to 18 mbits/s in slave and master modes in full- duplex and half-duplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. two standard i 2 s interfaces (multiplexed with spi1 and spi2 respectively) supporting four different audio standards can operate as master or slave at half-duplex communication mode. they can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. audio sampling frequency from 8 khz up to 192 khz can be set by an 8-bit programmable linear prescaler. when operating in master mode, they can output a clock for an external audio component at 256 times the sampling frequency. both spi1 and spi2 are identical and implement the set of features shown in the following table. smartcard mode x single-wire half-duplex communication x x irda sir endec block x lin mode x dual clock domain and wakeup from stop mode x receiver timeout interrupt x modbus communication x auto baud rate detection x driver enable x x 1. x = supported. table 10. stm32f071xx usart implementation (continued) usart modes/features (1) usart1 and usart2 usart3 and usart4 table 11. stm32f071xx spi/i2s implementation spi features (1) 1. x = supported. spi1 and spi2 hardware crc calculation x rx/tx fifo x nss pulse mode x i2s mode x ti mode x functional overview stm32f071xx 28/123 docid025451 rev 2 3.19 high-definition multimedia interface (hdmi) - consumer electronics control (cec) the device embeds a hdmi-cec controller that provides hardware support for the consumer electronics control (cec) protocol (supplement 1 to the hdmi standard). this protocol provides high-level control functions between all audiovisual products in an environment. it is specified to operate at low speeds with minimum processing and memory overhead. it has a clock domain independent from the cpu clock, allowing the hdmi_cec controller to wakeup the mcu from stop mode on data reception. 3.20 clock recovery system (crs) the stm32f071xx embeds a special block which allows automatic trimming of the internal 48 mhz oscillator to guarantee its optimal accuracy over the whole device operational range. this automatic trimming is based on the external synchronization signal, which could be either derived from lse oscillator, from an external signal on crs_sync pin or generated by user software. for faster lock-in during startup it is also possible to combine automatic trimming with manual trimming action. 3.21 serial wire debug port (sw-dp) an arm sw-dp interface is provided to allow a serial wire debugging tool to be connected to the mcu. docid025451 rev 2 29/123 stm32f071xx pinouts and pin descriptions 39 4 pinouts and pin descriptions figure 3. ufbga100 package ballout (top view) 0 6 9 $ % ( ' & ) * + - . / 0 3 ( 3 & 3 & 3 ( 3 & 3 ) 9 6 6 $ 3 ) 9 ' ' $ 3 ( 3 ( 3 ( 3 ( 9 % $ 7 3 ) 3 ) 1 5 6 7 3 & 3 & 3 $ 3 $ 3 % 3 ( 3 % 9 6 6 1 & 9 ' ' 3 & 3 $ 3 $ 3 $ % 2 2 7 3 % 9 ' ' 3 $ 3 $ 3 $ 3 ' 3 % 3 % 3 & 3 & 3 % 3 ' 3 ' 3 % 3 % 3 % 3 ' 3 ( 3 ( 3 % 3 ' 3 ' 3 ' 3 ( 3 ( 3 $ 3 ' 3 ' 3 ' 3 ( 3 ( 3 $ 3 & 3 & 3 & 3 $ 3 ' 3 ' 3 % 3 % 3 ( 3 $ 3 & 3 ) 3 $ 3 & 3 ' 3 ' 3 % 3 % 3 ( 9 6 6 9 ' ' , 2 3 $ 3 $ 3 $ 3 & 3 & 3 ' 3 ' 3 % 3 % 3 ( 9 6 6 9 ' ' 3 & 3 ) 3 ) , 2 s l q v x s s o l h g e \ 9 ' ' , 2 pinouts and pin descriptions stm32f071xx 30/123 docid025451 rev 2 figure 4. lqfp100 100-pin package pinout (top view) 3 ( 3 ( 3 ( 3 ( 3 ( 9 % $ 7 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 3 ) 3 ) 3 ) 2 6 & b , 1 1 5 6 7 3 & 3 & 3 & 3 & 3 ) 9 6 6 $ 3 ) 9 ' ' $ 3 $ 3 $ 3 $ 9 ' ' , 2 9 6 6 3 ) 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 & 3 & 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 % 3 % 3 % 3 % 3 $ 9 6 6 9 ' ' 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 % 3 % 3 % 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 ( 3 % 3 % 9 6 6 9 ' ' 9 ' ' 9 6 6 3 ( 3 ( 3 % 3 % % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 ' 3 & 3 & 3 & 3 $ 3 $ 0 6 9 / 4 ) 3 3 & 3 ) 2 6 & b 2 8 7 * 0 q j o t v q q m j f e c z 7 % % * 0 docid025451 rev 2 31/123 stm32f071xx pinouts and pin descriptions 39 figure 5. lqfp64 64-pin package pinout (top view) figure 6. lqfp48 48-pin package pinout (top view) 9 % $ 7 3 & 2 6 & b , 1 3 ) 2 6 & b , 1 1 5 6 7 3 & 3 & 3 & 3 & 9 6 6 $ 9 ' ' $ 3 $ 3 $ 3 $ 9 ' ' 3 % 3 % % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 ' 3 & 3 & 3 & 3 $ 3 $ 9 ' ' , 2 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 & 3 & 3 % 3 % 3 % 3 % 3 $ 9 6 6 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 % 3 % 3 % 3 % 3 % / 4 ) 3 3 & 0 6 9 9 ' ' 9 6 6 9 ' ' 9 6 6 3 ) 2 6 & b 2 8 7 3 & 2 6 & b 2 8 7 * 0 q j o t v q q m j f e c z 7 % % * 0 / 4 ) 3 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 % 3 % 9 6 6 9 ' ' 9 ' ' , 2 9 6 6 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 % 9 % $ 7 1 5 6 7 9 6 6 $ 9 ' ' $ 3 $ 3 $ 3 $ 9 ' ' 9 6 6 3 % 3 % % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 $ 3 $ 0 6 9 3 & 3 & 2 6 & b , 1 3 ) 2 6 & b , 1 3 ) 2 6 & b 2 8 7 3 & 2 6 & b 2 8 7 * 0 q j o t v q q m j f e c z 7 % % * 0 pinouts and pin descriptions stm32f071xx 32/123 docid025451 rev 2 figure 7. ufqfpn48 48-pin package pinout (top view) figure 8. wlcsp49 49-pin package ballout (bottom view) 0 6 9 8 ) 4 ) 3 1 6 " ! 4 . 2 3 4 6 3 3 ! 6 $ $ ! 0 ! 0 ! 0 # 0 # / 3 # ? ) . 0 & / 3 # ? ) . 0 & / 3 # ? / 5 4 0 # / 3 # ? / 5 4 0 ! 0 ! 0 ! 0 ! 0 ! 0 " 0 " 0 " 0 " 0 " 6 3 3 6 $ $ 6 $ $ ) / 6 3 3 0 ! 0 ! 0 ! 0 ! 0 ! 0 ! 0 " 0 " 0 " 0 " 6 $ $ 6 3 3 0 " 0 " " / / 4 0 " 0 " 0 " 0 " 0 " 0 ! 0 ! 0 ! * 0 q j o t v q q m j f e c z 7 % % * 0 0 6 9 9 ' ' 9 6 6 % 2 2 7 3 % 3 % 3 $ 3 $ 9 6 6 9 ' ' , 2 3 $ 3 % 3 % 1 & 9 % $ 7 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 3 % 3 % 3 $ 3 $ 3 $ 3 ) 2 6 & b 2 8 7 3 & 3 % 9 6 6 3 $ 3 $ 3 ) 2 6 & b , 1 9 6 6 $ 3 $ 3 $ 3 % 3 % 3 % 1 5 6 7 3 % 9 ' ' 3 $ 3 $ 3 $ 3 $ 9 ' ' $ 3 % 3 % 3 % 3 % 3 % 3 $ 3 $ $ % & ' ( ) * ) / p i n s u p p l i e d b y 6 $ $ ) / docid025451 rev 2 33/123 stm32f071xx pinouts and pin descriptions 39 table 12. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o ftf 5 v tolerant i/o, fm+ capable tta 3.3 v tolerant i/o directly connected to adc tc standard 3.3 v i/o b dedicated boot0 pin rst bidirectional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset. pin functions alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabled through peripheral registers table 13. stm32f071xx pin definitions pin numbers pin name (function after reset) pin type i/o structure notes pin functions ufbga100 lqfp100 lqfp64 lqfp48/ufqfpn48 wlcsp49 alternate functions additional functions b2 1 - - - pe2 i/o ft tsc_g7_io1, tim3_etr - a1 2 - - - pe3 i/o ft tsc_g7_io2, tim3_ch1 - b1 3 - - - pe4 i/o ft tsc_g7_io3, tim3_ch2 - c2 4 - - - pe5 i/o ft tsc_g7_io4, tim3_ch3 - d2 5 - - - pe6 i/o ft tim3_ch4 wkup3, rtc_tamp3 e2 6 1 1 b7 vbat s backup power supply c1 7 2 2 d5 pc13 i/o tc (1) (2) - wkup2, rtc_tamp1, rtc_ts, rtc_out pinouts and pin descriptions stm32f071xx 34/123 docid025451 rev 2 d1 8 3 3 c7 pc14-osc32_in (pc14) i/o tc (1) (2) - osc32_in e1 9 4 4 c6 pc15- osc32_out (pc15) i/o tc (1) (2) - osc32_out f2 10 - - - pf9 i/o ft tim15_ch1 - g2 11 - - - pf10 i/o ft tim15_ch2 - f1 12 5 5 d7 pf0-osc_in (pf0) i ft crs_ sync osc_in g1 13 6 6 d6 pf1-osc_out (pf1) o ft - osc_out h2 14 7 7 e7 nrst i/o rst device reset input / internal reset output (active low) h1 15 8 - - pc0 i/o tta eventout adc_in10 j2 16 9 - - pc1 i/o tta eventout adc_in11 j3 17 10 - - pc2 i/o tta spi2_miso, i2s2_mck, eventout adc_in12 k2 18 11 - - pc3 i/o tta spi2_mosi, i2s2_sd, eventout adc_in13 j1 19 - - - pf2 i/o ft eventout wkup8 k1 20 12 8 e6 vssa s analog ground m1 21 13 9 f7 vdda s analog power supply l1 22 - - - pf3 i/o ft eventout l2 23 14 10 f6 pa0 i/o tta usart2_cts, tim2_ch1_etr, tsc_g1_io1, usart4_tx rtc_ tamp2, wkup1, comp1_out, adc_in0, comp1_inm6 m2 24 15 11 g7 pa1 i/o tta usart2_rts, tim2_ch2, tim15_ch1n, tsc_g1_io2, usart4_rx, eventout adc_in1, comp1_inp table 13. stm32f071xx pin definitions (continued) pin numbers pin name (function after reset) pin type i/o structure notes pin functions ufbga100 lqfp100 lqfp64 lqfp48/ufqfpn48 wlcsp49 alternate functions additional functions docid025451 rev 2 35/123 stm32f071xx pinouts and pin descriptions 39 k3 25 16 12 e5 pa2 i/o tta usart2_tx, tim2_ch3, tim15_ch1, tsc_g1_io3 adc_in2, comp2_out, comp2_inm6, wkup4 l3 26 17 13 e4 pa3 i/o tta usart2_rx,tim2_ch4, tim15_ch2, tsc_g1_io4 adc_in3, comp2_inp d3 27 18 - - vss s ground h3 28 19 - - vdd s digital power supply m3 29 20 14 g6 pa4 i/o tta spi1_nss, i2s1_ws, tim14_ch1, tsc_g2_io1, usart2_ck comp1_inm4, comp2_inm4, adc_in4, dac_out1 k4 30 21 15 f5 pa5 i/o tta spi1_sck, i2s1_ck, cec, tim2_ch1_etr, tsc_g2_io2 comp1_inm5, comp2_inm5, adc_in5, dac_out2 l4 31 22 16 f4 pa6 i/o tta spi1_miso, i2s1_mck, tim3_ch1, tim1_bkin, tim16_ch1, comp1_out, tsc_g2_io3, eventout, usart3_cts adc_in6 m4 32 23 17 f3 pa7 i/o tta spi1_mosi, i2s1_sd, tim3_ch2, tim14_ch1, tim1_ch1n, tim17_ch1, comp2_out, tsc_g2_io4, eventout adc_in7 k5 33 24 - - pc4 i/o tta eventout, usart3_tx adc_in14 l5 34 25 - - pc5 i/o tta tsc_g3_io1, usart3_rx adc_in15, wkup5 m5 35 26 18 g5 pb0 i/o tta tim3_ch3, tim1_ch2n, tsc_g3_io2, eventout, usart3_ck adc_in8 m6 36 27 19 g4 pb1 i/o tta tim3_ch4, usart3_rts, tim14_ch1, tim1_ch3n, tsc_g3_io3 adc_in9 l6 37 28 20 g3 pb2 i/o ft tsc_g3_io4 - table 13. stm32f071xx pin definitions (continued) pin numbers pin name (function after reset) pin type i/o structure notes pin functions ufbga100 lqfp100 lqfp64 lqfp48/ufqfpn48 wlcsp49 alternate functions additional functions pinouts and pin descriptions stm32f071xx 36/123 docid025451 rev 2 m7 38 - - - pe7 i/o ft tim1_etr - l7 39 - - - pe8 i/o ft tim1_ch1n - m8 40 - - - pe9 i/o ft tim1_ch1 - l8 41 - - - pe10 i/o ft tim1_ch2n - m9 42 - - - pe11 i/o ft tim1_ch2 - l9 43 - - - pe12 i/o ft spi1_nss, i2s1_ws, tim1_ch3n - m10 44 - - - pe13 i/o ft spi1_sck, i2s1_ck, tim1_ch3 - m11 45 - - - pe14 i/o ft spi1_miso, i2s1_mck, tim1_ch4 - m12 46 - - - pe15 i/o ft spi1_mosi, i2s1_sd, tim1_bkin - l10 47 29 21 e3 pb10 i/o ft spi2_sck, i2c2_scl, usart3_tx, cec, tsc_sync, tim2_ch3 - l11 48 30 22 g2 pb11 i/o ft usart3_rx, tim2_ch4, eventout, tsc_g6_io1, i2c2_sda - f12 49 31 23 d3 vss s ground g12 50 32 24 f2 vdd s digital power supply l12 51 33 25 e2 pb12 i/o ft tim1_bkin, tim15_bkin, spi2_nss, i2s2_ws, usart3_ck, tsc_g6_io2, eventout - k12 52 34 26 g1 pb13 i/o ftf spi2_sck, i2s2_ck, i2c2_scl, usart3_cts, tim1_ch1n, tsc_g6_io3 - k11 53 35 27 f1 pb14 i/o ftf spi2_miso, i2s2_mck, i2c2_sda, usart3_rts, tim1_ch2n, tim15_ch1, tsc_g6_io4 - table 13. stm32f071xx pin definitions (continued) pin numbers pin name (function after reset) pin type i/o structure notes pin functions ufbga100 lqfp100 lqfp64 lqfp48/ufqfpn48 wlcsp49 alternate functions additional functions docid025451 rev 2 37/123 stm32f071xx pinouts and pin descriptions 39 k10 54 36 28 e1 pb15 i/o ft spi2_mosi, i2s2_sd, tim1_ch3n, tim15_ch1n, tim15_ch2 wkup7, rtc_refin k9 55 - - - pd8 i/o ft usart3_tx - k8 56 - - - pd9 i/o ft usart3_rx - j12 57 - - - pd10 i/o ft usart3_ck - j11 58 - - - pd11 i/o ft usart3_cts - j10 59 - - - pd12 i/o ft usart3_rts, tsc_g8_io1 - h12 60 - - - pd13 i/o ft tsc_g8_io2 - h11 61 - - - pd14 i/o ft tsc_g8_io3 - h10 62 - - - pd15 i/o ft tsc_g8_io4, crs_sync - e12 63 37 - - pc6 i/o ft (3) tim3_ch1 - e11 64 38 - - pc7 i/o ft (3) tim3_ch2 - e10 65 39 - - pc8 i/o ft (3) tim3_ch3 - d12 66 40 - - pc9 i/o ft (3) tim3_ch4 - d11 67 41 29 d1 pa8 i/o ft (3) usart1_ck, tim1_ch1, eventout, mco, crs_sync - d10 68 42 30 d2 pa9 i/o ft (3) usart1_tx, tim1_ch2, tim15_bkin, tsc_g4_io1 - c12 69 43 31 c2 pa10 i/o ft (3) usart1_rx, tim1_ch3, tim17_bkin, tsc_g4_io2 - b12 70 44 32 c1 pa11 i/o ft (3) usart1_cts, tim1_ch4, comp1_out, tsc_g4_io3, eventout a12 71 45 33 c3 pa12 i/o ft (3) usart1_rts, tim1_etr, comp2_out, tsc_g4_io4, eventout a11 72 46 34 b3 pa13 i/o ft (3) (4) ir_out, swdio - table 13. stm32f071xx pin definitions (continued) pin numbers pin name (function after reset) pin type i/o structure notes pin functions ufbga100 lqfp100 lqfp64 lqfp48/ufqfpn48 wlcsp49 alternate functions additional functions pinouts and pin descriptions stm32f071xx 38/123 docid025451 rev 2 c11 73 - - - pf6 i/o ft (3) -- f11 74 47 35 b1 vss s ground g11 75 48 36 b2 vddio2 s digital power supply a10 76 49 37 a1 pa14 i/o ft (3) (4) usart2_tx, swclk - a9 77 50 38 a2 pa15 i/o ft (3) spi1_nss, i2s1_ws, usart2_rx, usart4_rts, tim2_ch1_etr, eventout - b11 78 51 - - pc10 i/o ft (3) usart3_tx, usart4_tx - c10 79 52 - - pc11 i/o ft (3) usart3_rx, usart4_rx - b10 80 53 - - pc12 i/o ft (3) usart3_ck, usart4_ck - c9 81 - - - pd0 i/o ft (3) spi2_nss, i2s2_ws - b9 82 - - - pd1 i/o ft (3) spi2_sck, i2s2_ck - c8 83 54 - - pd2 i/o ft (3) usart3_rts, tim3_etr - b8 84 - - - pd3 i/o ft spi2_miso, i2s2_mck, usart2_cts - b7 85 - - - pd4 i/o ft spi2_mosi, i2s2_sd, usart2_rts - a6 86 - - - pd5 i/o ft usart2_tx - b6 87 - - - pd6 i/o ft usart2_rx - a5 88 - - - pd7 i/o ft usart2_ck - a8 89 55 39 a3 pb3 i/o ft spi1_sck, i2s1_ck, tim2_ch2, tsc_g5_io1, eventout - a7 90 56 40 a4 pb4 i/o ft spi1_miso, i2s1_mck, tim17_bkin, tim3_ch1, tsc_g5_io2, eventout - c5 91 57 41 b4 pb5 i/o ft spi1_mosi, i2s1_sd, i2c1_smba, tim16_bkin, tim3_ch2 wkup6 table 13. stm32f071xx pin definitions (continued) pin numbers pin name (function after reset) pin type i/o structure notes pin functions ufbga100 lqfp100 lqfp64 lqfp48/ufqfpn48 wlcsp49 alternate functions additional functions docid025451 rev 2 39/123 stm32f071xx pinouts and pin descriptions 39 b5 92 58 42 c4 pb6 i/o ftf i2c1_scl, usart1_tx, tim16_ch1n, tsc_g5_i03 - b4 93 59 43 d4 pb7 i/o ftf i2c1_sda, usart1_rx, usart4_cts, tim17_ch1n, tsc_g5_io4 - a4 94 60 44 a5 boot0 i b boot memory selection a3 95 61 45 b5 pb8 i/o ftf i2c1_scl, cec, tim16_ch1, tsc_sync - b3 96 62 46 c5 pb9 i/o ftf spi2_nss, i2s2_ws, i2c1_sda, ir_out, tim17_ch1, eventout - c3 97 - - - pe0 i/o ft eventout, tim16_ch1 - a2 98 - - - pe1 i/o ft eventout, tim17_ch1 - d3 99 63 47 a6 vss s ground c4 100 64 48 a7 vdd s digital power supply 1. pc13, pc14 and pc15 are supplied through the power switch. since the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf. - these gpios must not be used as current sources (e.g. to drive an led). 2. after the first rtc domain power-up, pc13, pc14 and pc15 operate as gpios. their function then depends on the content of the rtc registers which are not reset by the system reset. for details on how to manage these gpios, refer to the rtc domain and rtc register descriptions in the reference manual. 3. pc6, pc7, pc8, pc9, pa8, pa9, pa10, pa11, pa12, pa13, pf6, pa14, pa15, pc10, pc11, pc12, pd0, pd1 and pd2 i/os are supplied by vddio2. 4. after reset, these pins are configured as swdio and swclk alternate functions, and the internal pull-up on the swdio pin and the internal pull-down on the swclk pin are activated. table 13. stm32f071xx pin definitions (continued) pin numbers pin name (function after reset) pin type i/o structure notes pin functions ufbga100 lqfp100 lqfp64 lqfp48/ufqfpn48 wlcsp49 alternate functions additional functions stm32f071xx 40/123 docid025451 rev 2 table 14. alternate functions selected through gpioa_afr registers for port a pin name af0 af1 af2 af3 af4 af5 af6 af7 pa0 usart2_cts tim2_ch1_etr tsc_g1_io1 usart4_tx comp1_out pa1 eventout usart2_rts tim2_ch2 tsc_g1_io2 usart4_rx tim15_ch1n pa2 tim15_ch1 usart2_tx tim2_ch3 tsc_g1_io3 comp2_out pa3 tim15_ch2 usart2_rx tim2_ch4 tsc_g1_io4 pa4 spi1_nss, i2s1_ws usart2_ck tsc_g2_io1 tim14_ch1 pa5 spi1_sck, i2s1_ck cec tim2_ch1_etr tsc_g2_io2 pa6 spi1_miso, i2s1_mck tim3_ch1 tim1_bkin tsc_g2_io3 usart3_cts tim16_ch1 eventout comp1_out pa7 spi1_mosi, i2s1_sd tim3_ch2 tim1_ch1n tsc_g2_io4 tim14_ch1 tim17_ch1 eventout comp2_out pa8 mco usart1_ck tim1_ch1 eventout crs_sync pa9 tim15_bkin usart1_tx tim1_ch2 tsc_g4_io1 pa10 tim17_bkin usart1_rx tim1_ch3 tsc_g4_io2 pa11 eventout usart1_cts tim1_ch4 tsc_g4_io3 comp1_out pa12 eventout usart1_rts tim1_etr tsc_g4_io4 comp2_out pa13 swdio ir_out pa14 swclk usart2_tx pa15 spi1_nss, i2s1_ws usart2_rx tim2_ch1_etr eventout usart4_rts stm32f071xx docid025451 rev 2 41/123 table 15. alternate functions selected through gpiob_afr registers for port b pin name af0 af1 af2 af3 af4 af5 pb0 eventout tim3_ch3 tim1_ch2n tsc_g3_io2 usart3_ck pb1 tim14_ch1 tim3_ch4 tim1_ch3n tsc_g3_io3 usart3_rts pb2 tsc_g3_io4 pb3 spi1_sck, i2s1_ck eventout tim2_ch2 tsc_g5_io1 pb4 spi1_miso, i2s1_mck tim3_ch1 eventout tsc_g5_io2 tim17_bkin pb5 spi1_mosi, i2s1_sd tim3_ch2 tim16_bkin i2c1_smba pb6 usart1_tx i2c1_scl tim16_ch1n tsc_g5_io3 pb7 usart1_rx i2c1_sda tim17_ch1n tsc_g5_io4 usart4_cts pb8 cec i2c1_scl tim16_ch1 tsc_sync pb9 ir_out i2c1_sda tim17_ch1 eventout spi2_nss, i2s2_ws pb10 cec i2c2_scl tim2_ch3 tsc_sync usart3_tx spi2_sck, i2s2_ck pb11 eventout i2c2_sda tim2_ch4 tsc_g6_io1 usart3_rx pb12 spi2_nss, i2s2_ws eventout tim1_bkin tsc_g6_io2 usart3_ck tim15_bkin pb13 spi2_sck, i2s2_ck tim1_ch1n tsc_g6_io3 usart3_cts i2c2_scl pb14 spi2_miso, i2s2_mck tim15_ch1 tim1_ch2n tsc_g6_io4 usart3_rts i2c2_sda pb15 spi2_mosi, i2s2_sd tim15_ch2 tim1_ch3n tim15_ch1n stm32f071xx 42/123 docid025451 rev 2 table 16. alternate functions selected through gpioc_afr registers for port c pin name af0 af1 pc0 eventout - pc1 eventout - pc2 eventout spi2_miso, i2s2_mck pc3 eventout spi2_mosi, i2s2_sd pc4 eventout usart3_tx pc5 tsc_g3_io1 usart3_rx pc6 tim3_ch1 - pc7 tim3_ch2 - pc8 tim3_ch3 - pc9 tim3_ch4 - pc10 usart4_tx usart3_tx pc11 usart4_rx usart3_rx pc12 usart4_ck usart3_ck pc13 - - pc14 - - pc15 - - table 17. alternate functions selected through gpiod_afr registers for port d pin name af0 af1 pd0 - spi2_nss, i2s2_ws pd1 - spi2_sck, i2s2_ck pd2 tim3_etr usart3_rts pd3 usart2_cts spi2_miso, i2s2_mck pd4 usart2_rts spi2_mosi, i2s2_sd pd5 usart2_tx - pd6 usart2_rx - pd7 usart2_ck - pd8 usart3_tx - pd9 usart3_rx - pd10 usart3_ck - pd11 usart3_cts - pd12 usart3_rts tsc_g8_io1 pd13 - tsc_g8_io2 pd14 - tsc_g8_io3 pd15 crs_sync tsc_g8_io4 docid025451 rev 2 43/123 stm32f071xx 43 table 18. alternate functions selected through gpioe_afr registers for port e pin name af0 af1 pe0 tim16_ch1 eventout pe1 tim17_ch1 eventout pe2 tim3_etr tsc_g7_io1 pe3 tim3_ch1 tsc_g7_io2 pe4 tim3_ch2 tsc_g7_io3 pe5 tim3_ch3 tsc_g7_io4 pe6 tim3_ch4 - pe7 tim1_etr - pe8 tim1_ch1n - pe9 tim1_ch1 - pe10 tim1_ch2n - pe11 tim1_ch2 - pe12 tim1_ch3n spi1_nss, i2s1_ws pe13 tim1_ch3 spi1_sck, i2s1_ck pe14 tim1_ch4 spi1_miso, i2s1_mck pe15 tim1_bkin spi1_mosi, i2s1_sd table 19. alternate functions available on port f pin name af pf0 crs_sync pf1 - pf2 eventout pf3 eventout pf6 - pf9 tim15_ch1 pf10 tim15_ch2 memory mapping stm32f071xx 44/123 docid025451 rev 2 5 memory mapping figure 9. stm32f071xx memory map 2 e s e r v e d ! ( " x & & & & & & & & 0 e r i p h e r a l s 3 2 ! - & l a s h m e m o r y r e s e r v e d 3 y s t e m m e m o r y / p t i o n b y t e s # o r t e x - ) n t e r n a l 0 e r i p h e r a l s x % - 3 6 ' m b t i t z t u f n n f n p s z p s 4 3 " . e f q f o e j o h p o # 0 0 5 d p o g j h v s b u j p o x x % x # x ! x x x x x y x x & & & # x & & & & x & & & & & & & x r e s e r v e d # / $ % " 1 # " 1 # r e s e r v e d x x x x r e s e r v e d x " ) # x r e s e r v e d x & & x & & docid025451 rev 2 45/123 stm32f071xx memory mapping 46 table 20. stm32f071xx peripheral register boundary addresses bus boundary address size peripheral 0x4800 1800 - 0x5fff ffff ~384 mb reserved ahb2 0x4800 1400 - 0x4800 17ff 1 kb gpiof 0x4800 1000 - 0x4800 13ff 1 kb gpioe 0x4800 0c00 - 0x4800 0fff 1 kb gpiod 0x4800 0800 - 0x4800 0bff 1 kb gpioc 0x4800 0400 - 0x4800 07ff 1 kb gpiob 0x4800 0000 - 0x4800 03ff 1 kb gpioa 0x4002 4400 - 0x47ff ffff ~128 mb reserved ahb1 0x4002 4000 - 0x4002 43ff 1 kb tsc 0x4002 3400 - 0x4002 3fff 3 kb reserved 0x4002 3000 - 0x4002 33ff 1 kb crc 0x4002 2400 - 0x4002 2fff 3 kb reserved 0x4002 2000 - 0x4002 23ff 1 kb flash interface 0x4002 1400 - 0x4002 1fff 3 kb reserved 0x4002 1000 - 0x4002 13ff 1 kb rcc 0x4002 0400 - 0x4002 0fff 3 kb reserved 0x4002 0000 - 0x4002 03ff 1 kb dma 0x4001 8000 - 0x4001 ffff 32 kb reserved apb 0x4001 5c00 - 0x4001 7fff 9 kb reserved 0x4001 5800 - 0x4001 5bff 1 kb dbgmcu 0x4001 4c00 - 0x4001 57ff 3 kb reserved 0x4001 4800 - 0x4001 4bff 1 kb tim17 0x4001 4400 - 0x4001 47ff 1 kb tim16 0x4001 4000 - 0x4001 43ff 1 kb tim15 0x4001 3c00 - 0x4001 3fff 1 kb reserved 0x4001 3800 - 0x4001 3bff 1 kb usart1 0x4001 3400 - 0x4001 37ff 1 kb reserved 0x4001 3000 - 0x4001 33ff 1 kb spi1/i2s1 0x4001 2c00 - 0x4001 2fff 1 kb tim1 0x4001 2800 - 0x4001 2bff 1 kb reserved 0x4001 2400 - 0x4001 27ff 1 kb adc 0x4001 0800 - 0x4001 23ff 7 kb reserved 0x4001 0400 - 0x4001 07ff 1 kb exti 0x4001 0000 - 0x4001 03ff 1 kb syscfg + comp 0x4000 8000 - 0x4000 ffff 32 kb reserved memory mapping stm32f071xx 46/123 docid025451 rev 2 apb 0x4000 7c00 - 0x4000 7fff 1 kb reserved 0x4000 7800 - 0x4000 7bff 1 kb cec 0x4000 7400 - 0x4000 77ff 1 kb dac 0x4000 7000 - 0x4000 73ff 1 kb pwr 0x4000 6c00 - 0x4000 6fff 1 kb crs 0x4000 5c00 - 0x4000 6bff 4 kb reserved 0x4000 5800 - 0x4000 5bff 1 kb i2c2 0x4000 5400 - 0x4000 57ff 1 kb i2c1 0x4000 5000 - 0x4000 53ff 1 kb reserved 0x4000 4c00 - 0x4000 4fff 1 kb usart4 0x4000 4800 - 0x4000 4bff 1 kb usart3 0x4000 4400 - 0x4000 47ff 1 kb usart2 0x4000 3c00 - 0x4000 43ff 2 kb reserved 0x4000 3800 - 0x4000 3bff 1 kb spi2 0x4000 3400 - 0x4000 37ff 1 kb reserved 0x4000 3000 - 0x4000 33ff 1 kb iwdg 0x4000 2c00 - 0x4000 2fff 1 kb wwdg 0x4000 2800 - 0x4000 2bff 1 kb rtc 0x4000 2400 - 0x4000 27ff 1 kb reserved 0x4000 2000 - 0x4000 23ff 1 kb tim14 0x4000 1800 - 0x4000 1fff 2 kb reserved 0x4000 1400 - 0x4000 17ff 1 kb tim7 0x4000 1000 - 0x4000 13ff 1 kb tim6 0x4000 0800 - 0x4000 0fff 2 kb reserved 0x4000 0400 - 0x4000 07ff 1 kb tim3 0x4000 0000 - 0x4000 03ff 1 kb tim2 table 20. stm32f071xx peripheral register boundary addresses (continued) bus boundary address size peripheral docid025451 rev 2 47/123 stm32f071xx electrical characteristics 99 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ? ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = v dda = 3.3 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ? ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 10 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 11 . figure 10. pin loading conditions figure 11. pin input voltage - 3 6 & s ) - # 5 p i n - 3 6 - # 5 p i n 6 ) . electrical characteristics stm32f071xx 48/123 docid025451 rev 2 6.1.6 power supply scheme figure 12. power supply scheme caution: each power supply pair (v dd /v ss , v dda /v ssa etc.) must be decoupled with filtering ceramic capacitors as shown above. these capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the pcb to ensure the good functionality of the device. 9 ' ' , 2 9 ' ' 0 6 y 9 / h y h o v k l i w h u , 2 o r j l f . h u q h o o r j l f & 3 8 ' l j l w d o 0 h p r u l h v % d f n x s f l u f x l w u \ / 6 ( 5 7 & % d f n x s u h j l v w h u v , 1 2 8 7 5 h j x o d w r u * 3 , 2 v 9 , 1 2 8 7 * 3 , 2 v [ q ) [ ? ) q ) / h y h o v k l i w h u , 2 o r j l f ? ) 9 ' ' , 2 9 6 6 [ 9 6 6 [ 9 ' ' 9 % $ 7 9 & 2 5 ( 3 r z h u v z l w f k 9 ' ' , 2 9 ' ' , 2 $ ' & ' $ & $ q d o r j 5 & v 3 / / ? 9 5 ( ) 9 5 ( ) 9 ' ' $ q ) ? ) 9 ' ' $ 9 6 6 $ docid025451 rev 2 49/123 stm32f071xx electrical characteristics 99 6.1.7 current consumption measurement figure 13. current consumption measurement scheme 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 21: voltage characteristics , table 22: current characteristics and table 23: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. - 3 6 6 " ! 4 6 $ $ 6 $ $ ! ) $ $ ) $ $ ! * % % @ 7 # " 5 6 $ $ ) / table 21. voltage characteristics (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. symbol ratings min max unit v ddx ?v ss external main supply voltage (including v dda , v dd , v ddio2 and v bat ) ?0.3 4.0 v v dd ?v dda allowed voltage difference for v dd > v dda - 0.4 v v in (2) 2. v in maximum must always be respected. refer to table 22: current characteristics for the maximum allowed injected current values. input voltage on ft and ftf pins v ss ? 0.3 v ddiox + 4.0 v input voltage on tta pins v ss ? 0.3 4.0 v input voltage on any other pin v ss ?? 0.3 4.0 v | ? v ddx | variations between different v dd power pins - 50 mv |v ssx ?? v ss | variations between all the different ground pins -50mv v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.12: electrical sensitivity characteristics electrical characteristics stm32f071xx 50/123 docid025451 rev 2 table 22. current characteristics symbol ratings max. unit ? i vdd total current into sum of all vdd power lines (source) (1) 120 ma ? i vss total current out of sum of all vss ground lines (sink) (1) -120 i vdd(pin) maximum current into each vdd power pin (source) (1) 100 i vss(pin) maximum current out of each vss ground pin (sink) (1) -100 i io(pin) output current sunk by any i/o and control pin 25 output current source by any i/o and control pin -25 ? i io(pin) total output current sunk by sum of all ios and control pins (2) 80 total output current sourced by sum of all ios and control pins (2) -80 total output current sourced by sum of all ios supplied by vddio2 -40 i inj(pin) (3) injected current on ft, ftf and b pins -5/+0 (4) injected current on tc and rst pin 5 injected current on tta pins (5) 5 ? i inj(pin) total injected current (sum of all i/o and control pins) (6) 25 1. all main power (vdd, vdda) and ground (vss, vssa) pins must always be connected to the external power supply, in the permitted range. 2. this current consumption must be correctly distributed over all i/os and control pins. the total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count qfp packages. 3. a positive injection is induced by v in > v ddiox while a negative injection is induced by v in < v ss . i inj(pin) must never be exceeded. refer to table 21: voltage characteristics for the maximum allowed input voltage values. 4. positive injection is not possible on these i/os and does not occur for input voltages lower than the specified maximum value. 5. on these i/os, a positive injection is induced by v in > v dda . negative injection disturbs the analog performance of the device. see note (2) below table 60: adc accuracy . 6. when several inputs are submitted to a current injection, the maximum ? i inj(pin) is the absolute sum of the positive and negative injected currents (instantaneous values). table 23. thermal characteristics symbol ratings value unit t stg storage temperature range ?65 to +150 c t j maximum junction temperature 150 c docid025451 rev 2 51/123 stm32f071xx electrical characteristics 99 6.3 operating conditions 6.3.1 general operating conditions table 24. general operating conditions symbol parameter conditions min max unit f hclk internal ahb clock frequency 0 48 mhz f pclk internal apb clock frequency 0 48 v dd standard operating voltage 2 3.6 v v ddio2 i/o supply voltage must not be supplied if v dd is not present 1.65 3.6 v v dda analog operating voltage (adc and dac not used) must have a potential equal to or higher than v dd 2 3.6 v analog operating voltage (adc and dac used) 2.4 3.6 v bat backup operating voltage 1.65 3.6 v v in i/o input voltage tc and rst i/o ?0.3 v ddiox +0.3 v tta i/o ?0.3 v dda +0.3 ft and ftf i/o ?0.3 5.5 (1) boot0 0 9.0 p d power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (2) ufbga100 - 364 mw lqfp100 - 476 lqfp64 - 455 lqfp48 - 370 ufqfpn48 - 625 wlcsp49 - 408 t a ambient temperature for the suffix 6 version maximum power dissipation ?40 85 c low power dissipation (3) ?40 105 ambient temperature for the suffix 7 version maximum power dissipation ?40 105 c low power dissipation (3) ?40 125 t j junction temperature range suffix 6 version ?40 105 c suffix 7 version ?40 125 1. to sustain a voltage higher than v ddiox +0.3 v, the internal pull-up/pull-down resistors must be disabled. 2. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax (see section 7.2: thermal characteristics ). 3. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax (see section 7.2: thermal characteristics ). electrical characteristics stm32f071xx 52/123 docid025451 rev 2 6.3.2 operating conditions at power-up / power-down the parameters given in table 25 are derived from tests performed under the ambient temperature condition summarized in table 24 . 6.3.3 embedded reset and power control block characteristics the parameters given in table 26 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 24: general operating conditions . table 25. operating conditions at power-up / power-down symbol parameter conditions min max unit t vdd v dd rise time rate 0 ? s/v v dd fall time rate 20 ? t vdda v dda rise time rate 0 ? v dda fall time rate 20 ? table 26. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v por/pdr (1) 1. the pdr detector monitors v dd and also v dda (if kept enabled in the option bytes). the por detector monitors only v dd . power on/power down reset threshold falling edge (2) 2. the product behavior is guaranteed by design down to the minimum v por/pdr value. 1.80 1.88 1.96 (3) 3. data based on characterization results, not tested in production. v rising edge 1.84 (3) 1.92 2.00 v v pdrhyst pdr hysteresis - 40 - mv t rsttempo (4) 4. guaranteed by design, not tested in production. reset temporization 1.50 2.50 4.50 ms table 27. programmable voltage detector characteristics symbol parameter conditions min typ max unit v pvd0 pvd threshold 0 rising edge 2.1 2.18 2.26 v falling edge 2 2.08 2.16 v v pvd1 pvd threshold 1 rising edge 2.19 2.28 2.37 v falling edge 2.09 2.18 2.27 v v pvd2 pvd threshold 2 rising edge 2.28 2.38 2.48 v falling edge 2.18 2.28 2.38 v v pvd3 pvd threshold 3 rising edge 2.38 2.48 2.58 v falling edge 2.28 2.38 2.48 v docid025451 rev 2 53/123 stm32f071xx electrical characteristics 99 6.3.4 embedded reference voltage the parameters given in table 28 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 24: general operating conditions . v pvd4 pvd threshold 4 rising edge 2.47 2.58 2.69 v falling edge 2.37 2.48 2.59 v v pvd5 pvd threshold 5 rising edge 2.57 2.68 2.79 v falling edge 2.47 2.58 2.69 v v pvd6 pvd threshold 6 rising edge 2.66 2.78 2.9 v falling edge 2.56 2.68 2.8 v v pvd7 pvd threshold 7 rising edge 2.76 2.88 3 v falling edge 2.66 2.78 2.9 v v pvdhyst (1) pvd hysteresis - 100 - mv i dd(pvd) pvd current consumption - 0.15 0.26 (1) a 1. guaranteed by design, not tested in production. table 27. programmable voltage detector characteristics (continued) symbol parameter conditions min typ max unit table 28. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.16 1.2 1.25 v ?40 c < t a < +85 c 1.16 1.2 1.24 (1) 1. data based on characterization results, not tested in production. v t s_vrefint adc sampling time when reading the internal reference voltage 4 (2) 2. guaranteed by design, not tested in production. -- s ? v refint internal reference voltage spread over the temperature range v dda = 3 v - - 10 (2) mv t coeff temperature coefficient - - 100 (2) ppm/c electrical characteristics stm32f071xx 54/123 docid025451 rev 2 6.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pin loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 13: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to coremark code. typical and maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in analog input mode ? all peripherals are disabled except when explicitly mentioned ? the flash memory access time is adjusted to the f hclk frequency: ? 0 wait state and prefetch off from 0 to 24 mhz ? 1 wait state and prefetch on above 24 mhz ? when the peripherals are enabled f pclk = f hclk the parameters given in table 29 to table 34 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 24: general operating conditions . table 29. typical and maximum current consumption from v dd supply at v dd = 3.6 v symbol parameter conditions f hclk all peripherals enabled all peripherals disabled unit typ max @ t a (1) typ max @ t a (1) 25 c 85 c 105 c 25 c 85 c 105 c i dd supply current in run mode, code executing from flash hsi48 48 mhz 24.3 26.9 27.2 27.9 13.1 14.8 14.9 15.5 ma hse bypass, pll on 48 mhz 24.1 26.8 27.0 27.7 13.0 14.6 14.8 15.4 32 mhz 16.0 18.3 18.6 19.2 8.76 9.56 9.73 10.6 24 mhz 12.3 13.7 14.3 14.7 7.36 7.94 8.37 8.81 hse bypass, pll off 8 mhz 4.52 5.25 5.28 5.61 2.89 3.17 3.26 3.34 1 mhz 1.25 1.39 1.58 1.87 0.93 1.06 1.15 1.34 hsi clock, pll on 48 mhz 24.1 27.1 27.6 27.8 12.9 14.7 14.9 15.5 32 mhz 16.1 18.2 18.9 19.3 8.82 9.69 9.83 10.7 24 mhz 12.4 14.0 14.4 14.8 7.31 7.92 8.34 8.75 hsi clock, pll off 8 mhz 4.52 5.25 5.35 5.61 2.87 3.16 3.25 3.33 docid025451 rev 2 55/123 stm32f071xx electrical characteristics 99 i dd supply current in run mode, code executing from ram hsi48 48 mhz 23.1 25.4 25.8 26.6 12.8 13.5 13.7 13.9 ma hse bypass, pll on 48 mhz 23.0 25.3 (2) 25.7 26.5 (2) 12.6 13.3 (2) 13.5 13.8 (2) 32 mhz 15.4 17.3 17.8 18.3 7.96 8.92 9.17 9.73 24 mhz 11.4 12.9 13.5 13.7 6.48 8.04 8.23 8.41 hse bypass, pll off 8 mhz 4.21 4.6 4.89 5.25 2.07 2.3 2.35 2.94 1 mhz 0.78 0.9 0.92 1.15 0.36 0.48 0.59 0.82 hsi clock, pll on 48 mhz 23.1 24.5 25.0 25.2 12.6 13.7 13.9 14.0 32 mhz 15.4 17.4 17.7 18.2 8.05 8.85 9.16 9.94 24 mhz 11.5 13.0 13.6 13.9 6.49 8.06 8.21 8.47 hsi clock, pll off 8 mhz 4.34 4.75 5.03 5.41 2.11 2.36 2.38 2.98 supply current in sleep mode, code executing from flash or ram hsi48 48 mhz 15.1 16.6 16.8 17.5 3.08 3.43 3.56 3.61 hse bypass, pll on 48 mhz 15.0 16.5 (2) 16.7 17.3 (2) 2.93 3.28 (2) 3.41 3.46 (2) 32 mhz 9.9 11.4 11.6 11.9 2.0 2.24 2.32 2.49 24 mhz 7.43 8.17 8.71 8.82 1.63 1.82 1.88 1.9 hse bypass, pll off 8 mhz 2.83 3.09 3.26 3.66 0.76 0.88 0.91 0.93 1 mhz 0.42 0.54 0.55 0.67 0.28 0.39 0.41 0.43 hsi clock, pll on 48 mhz 15.0 17.2 17.3 17.9 3.04 3.37 3.41 3.46 32 mhz 9.93 11.3 11.6 11.7 2.11 2.35 2.44 2.65 24 mhz 7.53 8.45 8.87 8.95 1.64 1.83 1.9 1.93 hsi clock, pll off 8 mhz 2.95 3.24 3.41 3.8 0.8 0.92 0.94 0.97 1. data based on characterization results, not tested in production unless otherwise specified. 2. data based on characterization results and tested in production (using one common test limit for sum of i dd and i dda ). table 29. typical and maximum current consumption from v dd supply at v dd = 3.6 v (continued) symbol parameter conditions f hclk all peripherals enabled all peripherals disabled unit typ max @ t a (1) typ max @ t a (1) 25 c 85 c 105 c 25 c 85 c 105 c electrical characteristics stm32f071xx 56/123 docid025451 rev 2 table 30. typical and maximum current consumption from the v dda supply symbol para- meter conditions (1) f hclk v dda = 2.4 v v dda = 3.6 v unit typ max @ t a (2) typ max @ t a (2) 25 c 85 c 105 c 25 c 85 c 105 c i dda supply current in run or sleep mode, code executing from flash or ram hsi48 48 mhz 311 326 334 343 322 337 345 354 a hse bypass, pll on 48 mhz 152 170 (3) 178 182 (3) 165 184 (3) 196 200 (3) 32 mhz 105 121 126 128 113 129 136 138 24 mhz 81.9 95.9 99.5 101 88.7 102 107 108 hse bypass, pll off 8 mhz 2.7 3.8 4.3 4.6 3.6 4.7 5.2 5.5 1 mhz 2.7 3.8 4.3 4.6 3.6 4.7 5.2 5.5 hsi clock, pll on 48 mhz 223 244 255 260 245 265 279 284 32 mhz 176 195 203 206 193 212 221 224 24 mhz 154 171 178 181 168 185 192 195 hsi clock, pll off 8 mhz 74.2 83.4 86.4 87.3 83.4 92.5 95.3 96.6 1. current consumption from the v dda supply is independent of whether the digital peripherals are enabled or disabled, being in run or sleep mode or executing from flash or ram. furthermore, when the pll is off, i dda is independent from the frequency. 2. data based on characterization results, not tested in production unless otherwise specified. 3. data based on characterization results and tested in production (using one common test limit for sum of i dd and i dda ). docid025451 rev 2 57/123 stm32f071xx electrical characteristics 99 table 31. typical and maximum consumption in stop and standby modes sym- bol para- meter conditions typ @v dd (v dd = v dda ) max (1) unit 2.0 v 2.4 v 2.7 v 3.0 v 3.3 v 3.6 v t a = 25 c t a = 85 c t a = 105 c i dd supply current in stop mode regulator in run mode, all oscillators off 15.4 15.5 15.6 15.7 15.8 15.9 23 (2) 49 68 (2) a regulator in low- power mode, all oscillators off 3.2 3.3 3.4 3.5 3.6 3.7 8 (2) 33 51 (2) supply current in standby mode lsi on and iwdg on 0.8 1.0 1.1 1.2 1.3 1.4 - - - lsi off and iwdg off 0.6 0.7 0.9 0.9 1.0 1.1 2.1 (2) 2.6 3.1 (2) i dda supply current in stop mode v dda monitoring on regulator in run mode, all oscillators off 2.1 2.2 2.3 2.5 2.6 2.8 3.5 (2) 3.6 4.6 (2) regulator in low-power mode, all oscillators off 2.1 2.2 2.3 2.5 2.6 2.8 3.5 (2) 3.6 4.6 (2) supply current in standby mode lsi on and iwdg on 2.5 2.7 2.8 3.0 3.2 3.5 - - - lsi off and iwdg off 1.9 2.1 2.2 2.3 2.5 2.6 3.5 (2) 3.6 4.6 (2) supply current in stop mode v dda monitoring off regulator in run mode, all oscillators off 1.3 1.3 1.4 1.4 1.5 1.5 - - - regulator in low-power mode, all oscillators off 1.3 1.3 1.4 1.4 1.5 1.5 - - - supply current in standby mode lsi on and iwdg on 1.7 1.8 1.9 2.0 2.1 2.2 - - - lsi off and iwdg off 1.2 1.2 1.2 1.3 1.3 1.4 - - - 1. data based on characterization results, not tested in production unless otherwise specified. 2. data based on characterization results and tested in production (using one common test limit for sum of i dd and i dda ). electrical characteristics stm32f071xx 58/123 docid025451 rev 2 typical current consumption the mcu is placed under the following conditions: ? v dd =v dda =3.3 v ? all i/o pins are in analog input configuration ? the flash access time is adjusted to f hclk frequency: ? 0 wait state and prefetch off from 0 to 24 mhz ? 1 wait state and prefetch on above 24 mhz ? when the peripherals are enabled, f pclk = f hclk ? pll is used for frequencies greater than 8 mhz ? ahb prescaler of 2, 4, 8 and 16 is used for the frequencies 4 mhz, 2 mhz, 1 mhz and 500 khz respectively table 32. typical and maximum current consumption from the v bat supply symbol parameter conditions typ @ v bat max (1) unit = 1.65 v = 1.8 v = 2.4 v = 2.7 v = 3.3 v = 3.6 v t a = 25 c t a = 85 c t a = 105 c i dd _ vbat rtc domain supply current lse & rtc on; ?xtal mode?: lower driving capability; lsedrv[1:0] = '00' 0.5 0.6 0.7 0.8 1.1 1.2 tbd tbd tbd a lse & rtc on; ?xtal mode? higher driving capability; lsedrv[1:0] = '11' 0.8 0.9 1.1 1.2 1.4 1.6 tbd tbd tbd 1. data based on characterization results, not tested in production. docid025451 rev 2 59/123 stm32f071xx electrical characteristics 99 table 33. typical current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk typ unit peripherals enabled peripherals disabled i dd supply current in run mode from v dd supply running from hse crystal clock 8 mhz, code executing from flash 48 mhz 23.5 13.5 ma 36 mhz 18.3 10.5 32 mhz 16.0 9.6 24 mhz 12.3 7.6 16 mhz 8.6 5.3 8 mhz 4.8 3.1 4 mhz 3.1 2.1 2 mhz 2.1 1.6 1 mhz 1.6 1.3 500 khz 1.3 1.2 i dda supply current in run mode from v dda supply 48 mhz 163.3 163.3 a 36 mhz 124.3 124.3 32 mhz 111.9 111.9 24 mhz 87.1 87.1 16 mhz 62.5 62.5 8 mhz 2.5 2.5 4 mhz 2.5 2.5 2 mhz 2.5 2.5 1 mhz 2.5 2.5 500 khz 2.5 2.5 electrical characteristics stm32f071xx 60/123 docid025451 rev 2 table 34. typical current consumption in sleep mode, code running from flash symbol parameter conditions f hclk typ unit peripherals enabled peripherals disabled i dd supply current in sleep mode from v dd supply running from hse crystal clock 8 mhz, code executing from flash 48 mhz 14.6 3.5 ma 36 mhz 11.1 2.9 32 mhz 10.0 2.7 24 mhz 7.8 2.2 16 mhz 5.5 1.7 8 mhz 3.1 1.2 4 mhz 2.2 1.1 2 mhz 1.6 1.0 1 mhz 1.4 1.0 500 khz 1.2 1.0 i dda supply current in sleep mode from v dda supply 48 mhz 163.3 163.3 a 36 mhz 124.3 124.3 32 mhz 111.9 111.9 24 mhz 87.1 87.1 16 mhz 62.5 62.5 8 mhz 2.5 2.5 4 mhz 2.5 2.5 2 mhz 2.5 2.5 1 mhz 2.5 2.5 500 khz 2.5 2.5 docid025451 rev 2 61/123 stm32f071xx electrical characteristics 99 i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up generate current consumption when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in table 54: i/o static characteristics . for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applied. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input value. unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by using pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption measured previously (see table 36: peripheral current consumption ), the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the i/o supply voltage to supply the i/o pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: where i sw is the current sunk by a switching i/o to charge/discharge the capacitive load v ddiox is the i/o supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext + c s c s is the pcb board capacitance including the pad pin. the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. i sw v ddiox f sw c ? ? = electrical characteristics stm32f071xx 62/123 docid025451 rev 2 table 35. switching output i/o current consumption symbol parameter conditions (1) 1. c s = 7 pf (estimated value). i/o toggling frequency (f sw ) typ unit i sw i/o current consumption v ddiox = 3.3 v c =c int 4 mhz 0.07 ma 8 mhz 0.15 16 mhz 0.31 24 mhz 0.53 48 mhz 0.92 v ddiox = 3.3 v c ext = 0 pf c = c int + c ext + c s 4 mhz 0.18 8 mhz 0.37 16 mhz 0.76 24 mhz 1.39 48 mhz 2.188 v ddiox = 3.3 v c ext = 10 pf c = c int + c ext + c s 4 mhz 0.32 8 mhz 0.64 16 mhz 1.25 24 mhz 2.23 48 mhz 4.442 v ddiox = 3.3 v c ext = 22 pf c = c int + c ext + c s 4 mhz 0.49 8 mhz 0.94 16 mhz 2.38 24 mhz 3.99 v ddiox = 3.3 v c ext = 33 pf c = c int + c ext + c s 4 mhz 0.64 8 mhz 1.25 16 mhz 3.24 24 mhz 5.02 v ddiox = 3.3 v c ext = 47 pf c = c int + c ext + c s c = c int 4 mhz 0.81 8 mhz 1.7 16 mhz 3.67 v ddiox = 2.4 v c ext = 47 pf c = c int + c ext + c s c = c int 4 mhz 0.66 8 mhz 1.43 16 mhz 2.45 24 mhz 4.97 docid025451 rev 2 63/123 stm32f071xx electrical characteristics 99 on-chip peripheral current consumption the current consumption of the on-chip peripherals is given in table 36 . the mcu is placed under the following conditions: ? all i/o pins are in analog mode ? all peripherals are disabled unless otherwise mentioned ? the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ? ambient operating temperature and supply voltage conditions summarized in table 21: voltage characteristics ? the power consumption of the digital part of the on-chip peripherals is given in table 35. the power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet. table 36. peripheral current consumption peripheral typical consumption at 25 c unit ahb busmatrix (1) 2.2 a/mhz crc 1.6 dma 5.7 flash interface 13.0 gpioa 8.2 gpiob 8.5 gpioc 2.3 gpiod 1.9 gpioe 2.2 gpiof 1.2 sram 0.9 tsc 5.0 all ahb peripherals 52.6 electrical characteristics stm32f071xx 64/123 docid025451 rev 2 6.3.6 wakeup time from low-power mode the wakeup times given in table 37 are the latency between the event and the execution of the first user instruction. the device goes in low-power mode after the wfe (wait for event) instruction, in the case of a wfi (wait for interruption) instruction, 16 cpu cycles apb apb-bridge (2) 2.8 a/mhz adc (3) 4.1 cec 1.5 crs 0.8 dac (3) 4.7 debug (mcu debug feature) 0.1 i2c1 3.9 i2c2 4.0 pwr 1.3 spi1 8.7 spi2 8.5 syscfg & comp 1.7 tim1 14.9 tim2 15.5 tim3 11.4 tim6 2.5 tim7 2.3 tim14 5.3 tim15 9.1 tim16 6.6 tim17 6.8 usart1 17.0 usart2 16.7 usart3 5.4 usart4 5.4 wwdg 1.4 all apb peripherals 182 1. the busmatrix is automatically active when at least one master is on (cpu, dma). 2. the apb bridge is automatically active when at least one peripheral is on on the bus. 3. the power consumption of the analog part (i dda ) of peripherals such as adc, dac, comparators, is not included. refer to the tables of characteristics in the subsequent sections. table 36. peripheral current consumption (continued) peripheral typical consumption at 25 c unit docid025451 rev 2 65/123 stm32f071xx electrical characteristics 99 must be added to the following timings due to the interrupt latency in the cortex m0 architecture. the sysclk clock source setting is kept unchanged after wakeup from sleep mode. after wakeup from stop or standby mode, sysclk takes the default setting: hsi 8 mhz. the wakeup source from sleep and stop mode is an exti line configured in event mode. the wakeup source from standby mode is the wkup1 pin (pa0). all timings are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 24: general operating conditions except when explicitly mentioned table 37. low-power mode wakeup timings symbol parameter conditions typ @v dd = v dda max unit = 2.0 v = 2.4 v = 2.7 v = 3 v = 3.3 v t wustop wakeup from stop mode regulator in run mode 3.2 3.1 2.9 2.9 2.8 5 s regulator in low power mode 7.0 5.8 5.2 4.9 4.6 9 t wustandby wakeup from standby mode 60.4 55.6 53.5 52 51 - t wusleep wakeup from sleep mode 4 sysclk cycles - electrical characteristics stm32f071xx 66/123 docid025451 rev 2 6.3.7 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillator is switched off and the input pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock input waveform is shown in figure 14: high-speed external clock source ac timing diagram . figure 14. high-speed external clock source ac timing diagram table 38. high-speed external user clock characteristics symbol parameter (1) conditions min typ max unit f hse_ext user external clock source frequency 1 8 32 mhz v hseh osc_in input pin high level voltage 0.7 v ddiox -v ddiox v v hsel osc_in input pin low level voltage v ss - 0.3 v ddiox t w(hseh) t w(hsel) osc_in high or low time 15 - - ns t r(hse) t f(hse) osc_in rise or fall time - - 20 1. guaranteed by design, not tested in production. - 3 6 6 ( 3 % ( t f ( 3 % 4 ( 3 % t t r ( 3 % 6 ( 3 % , t w ( 3 % ( t w ( 3 % , docid025451 rev 2 67/123 stm32f071xx electrical characteristics 99 low-speed external user clock generated from an external source in bypass mode the lse oscillator is switched off and the input pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock input waveform is shown in figure 15 . figure 15. low-speed external clock source ac timing diagram table 39. low-speed external user clock characteristics symbol parameter (1) conditions min typ max unit f lse_ext user external clock source frequency - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7 v ddiox -v ddiox v v lsel osc32_in input pin low level voltage v ss - 0.3 v ddiox t w(lseh) t w(lsel) osc32_in high or low time 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time - - 50 1. guaranteed by design, not tested in production. - 3 6 6 , 3 % ( t f , 3 % 4 , 3 % t t r , 3 % 6 , 3 % , t w , 3 % ( t w , 3 % , electrical characteristics stm32f071xx 68/123 docid025451 rev 2 high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 32 mhz crystal/ceramic resonator oscillator. all the information given in this paragraph are based on design simulation results obtained with typical external components specified in table 40 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 20 pf range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see figure 16 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the combined pin and board capacitance) when sizing c l1 and c l2 . note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. table 40. hse oscillator characteristics symbol parameter conditions (1) 1. resonator characteristics given by the crystal/ceramic resonator manufacturer. min (2) typ max (2) 2. guaranteed by design, not tested in production. unit f osc_in oscillator frequency 4 8 32 mhz r f feedback resistor - 200 - k ? i dd hse current consumption during startup (3) 3. this consumption level occurs during the first 2/3 of the t su(hse) startup time - 8.5 ma v dd = 3.3 v, rm = 30 ? , cl = 10 pf@8 mhz - 0.4 - v dd = 3.3 v, rm = 45 ? , cl = 10 pf@8 mhz - 0.5 - v dd = 3.3 v, rm = 30 ? , cl = 5 pf@32 mhz - 0.8 - v dd = 3.3 v, rm = 30 ? , cl = 10 pf@32 mhz -1- v dd = 3.3 v, rm = 30 ? , cl = 20 pf@32 mhz - 1.5 - g m oscillator transconductance startup 10 - - ma/v t su(hse) (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer startup time v dd is stabilized - 2 - ms docid025451 rev 2 69/123 stm32f071xx electrical characteristics 99 figure 16. typical application with an 8 mhz crystal 1. r ext value depends on the crystal characteristics. - 3 6 / 3 # ? / 5 4 / 3 # ? ) . f ( 3 % # , 2 & - ( z r e s o n a t o r 2 % 8 4 # , 2 e s o n a t o r w i t h i n t e g r a t e d c a p a c i t o r s " i a s c o n t r o l l e d g a i n electrical characteristics stm32f071xx 70/123 docid025451 rev 2 low-speed external clock generated from a crystal resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal resonator oscillator. all the information given in this paragraph are based on design simulation results obtained with typical external components specified in table 41 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com. table 41. lse oscillator characteristics (f lse = 32.768 khz) symbol parameter conditions (1) min (2) typ max (2) unit i dd lse current consumption lsedrv[1:0]=00 lower driving capability - 0.5 0.9 a lsedrv[1:0]= 01 medium low driving capability --1 lsedrv[1:0] = 10 medium high driving capability - - 1.3 lsedrv[1:0]=11 higher driving capability - - 1.6 g m oscillator transconductance lsedrv[1:0]=00 lower driving capability 5- - a/v lsedrv[1:0]= 01 medium low driving capability 8- - lsedrv[1:0] = 10 medium high driving capability 15 - - lsedrv[1:0]=11 higher driving capability 25 - - t su(lse) (3) startup time v dd is stabilized - 2 - s 1. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. 2. guaranteed by design, not tested in production. 3. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is measured for a standard crystal and it can vary significantly with the crystal manufacturer docid025451 rev 2 71/123 stm32f071xx electrical characteristics 99 figure 17. typical application with a 32.768 khz crystal note: an external resistor is not required between osc32_in and osc32_out and it is forbidden to add one. 0 6 9 2 6 & b 2 8 7 2 6 & b , 1 i / 6 ( & / n + ] u h v r q d w r u & / 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v ' u l y h s u r j u d p p d e o h d p s o l i l h u electrical characteristics stm32f071xx 72/123 docid025451 rev 2 6.3.8 internal clock source characteristics the parameters given in table 42 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 24: general operating conditions . the provided curves are characterization results, not tested in production. high-speed internal (hsi) rc oscillator figure 18. hsi oscillator accuracy characterization results table 42. hsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - 8 - mhz trim hsi user trimming step - - 1 (2) 2. guaranteed by design, not tested in production. % ducy (hsi) duty cycle 45 (2) -55 (2) % acc hsi accuracy of the hsi oscillator (factory calibrated) t a = ?40 to 105 c ?3.8 (3) 3. data based on characterization results, not tested in production. - 4.6 (3) % t a = ?10 to 85 c ?2.9 (3) - 2.9 (3) % t a = 0 to 70 c ?1.3 (3) - 2.2 (3) % t a = 25 c ?1 - 1 % t su(hsi) hsi oscillator startup time 1 (2) -2 (2) s i dda(hsi) hsi oscillator power consumption - 80 100 (2) a - 3 6 - ! 8 - ) . 4 ; ? # = ! docid025451 rev 2 73/123 stm32f071xx electrical characteristics 99 high-speed internal 14 mhz (hsi14) rc oscillator (dedicated to adc) figure 19. hsi14 oscillator accuracy characterization results table 43. hsi14 oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi14 frequency - 14 - mhz trim hsi14 user-trimming step - - 1 (2) 2. guaranteed by design, not tested in production. % ducy (hsi14) duty cycle 45 (2) -55 (2) % acc hsi14 accuracy of the hsi14 oscillator (factory calibrated) t a = ?40 to 105 c ?4.2 (3) 3. data based on characterization results, not tested in production. - 5.1 (3) % t a = ?10 to 85 c ?3.2 (3) - 3.1 (3) % t a = 0 to 70 c ?1.3 (3) - 2.2 (3) % t a = 25 c ?1 - 1 % t su(hsi14) hsi14 oscillator startup time 1 (2) -2 (2) s i dda(hsi14) hsi14 oscillator power consumption - 100 150 (2) a - 3 6 - ! 8 - ) . 4 ; ? # = ! electrical characteristics stm32f071xx 74/123 docid025451 rev 2 high-speed internal 48 mhz (hsi48) rc oscillator figure 20. hsi48 oscillator accuracy characterization results table 44. hsi48 oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi48 frequency - 48 - mhz trim hsi48 user-trimming step 0.09 (2) 0.14 0.2 (2) % ducy (hsi48) duty cycle 45 (2) 2. guaranteed by design, not tested in production. -55 (2) % acc hsi48 accuracy of the hsi48 oscillator (factory calibrated) t a = ?40 to 105 c -4.9 (3) 3. data based on characterization results, not tested in production. - 4.7 (3) % t a = ?10 to 85 c -4.1 (3) - 3.7 (3) % t a = 0 to 70 c -3.8 (3) - 3.4 (3) % t a = 25 c -2.8 - 2.9 % t su(hsi48) hsi48 oscillator startup time - - 6 (2) s i dda(hsi48) hsi48 oscillator power consumption - 312 350 (2) a - 3 6 - ! 8 - ) . 4 ; ? # = ! docid025451 rev 2 75/123 stm32f071xx electrical characteristics 99 low-speed internal (lsi) rc oscillator 6.3.9 pll characteristics the parameters given in table 46 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 24: general operating conditions . table 45. lsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi frequency 30 40 50 khz t su(lsi) (2) 2. guaranteed by design, not tested in production. lsi oscillator startup time - - 85 s i dda(lsi) (2) lsi oscillator power consumption - 0.75 1.2 a table 46. pll characteristics symbol parameter value unit min typ max f pll_in pll input clock (1) 1. take care to use the appropriate multiplier factors to obtain pll input clock values compatible with the range defined by f pll_out . 1 (2) 8.0 24 (2) mhz pll input clock duty cycle 40 (2) -60 (2) % f pll_out pll multiplier output clock 16 (2) - 48 mhz t lock pll lock time - - 200 (2) 2. guaranteed by design, not tested in production. s jitter pll cycle-to-cycle jitter - - 300 (2) ps electrical characteristics stm32f071xx 76/123 docid025451 rev 2 6.3.10 memory characteristics flash memory the characteristics are given at t a = ?40 to 105 c unless otherwise specified. 6.3.11 emc characteristics susceptibility tests are performed on a sample basis during device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on the device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure occurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 49 . they are based on the ems levels and classes defined in application note an1709. table 47. flash memory characteristics symbol parameter conditions min typ max (1) 1. guaranteed by design, not tested in production. unit t prog 16-bit programming time t a ??? ?40 to +105 c 40 53.5 60 s t erase page (2 kb) erase time t a ?? ?40 to +105 c 20 - 40 ms t me mass erase time t a ?? ?40 to +105 c 20 - 40 ms i dd supply current write mode - - 10 ma erase mode - - 12 ma v prog programming voltage 2 - 3.6 v table 48. flash memory endurance and data retention symbol parameter conditions min (1) 1. data based on characterization results, not tested in production. unit n end endurance t a = ?40 to +105 c 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over the whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20 docid025451 rev 2 77/123 stm32f071xx electrical characteristics 99 designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o ports). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. table 49. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd ?? 3.3 v, lqfp100, t a ?? +25 c, f hclk ?? 48 mhz, conforming to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd ??? 3.3 v, lqfp100, t a ?? +25 c, f hclk ?? 48 mhz, conforming to iec 61000-4-4 4b table 50. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/48 mhz s emi peak level v dd ?? 3.6 v, t a ?? 25 c, lqfp100 package compliant with iec 61967-2 0.1 to 30 mhz -3 db v 30 to 130 mhz 23 130 mhz to 1ghz 14 emi level 4 - electrical characteristics stm32f071xx 78/123 docid025451 rev 2 6.3.12 electrical sensitivity characteristics based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. static latch-up two complementary static tests are required on six parts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin. ? a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with eia/jesd 78a ic latch-up standard. 6.3.13 i/o current injection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v ddiox (for standard, 3.3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. table 51. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a ?? +25 c, conforming to jesd22-a114 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a ?? +25 c, conforming to ansi/esd stm5.3.1 ii 500 table 52. electrical sensitivities symbol parameter conditions class lu static latch-up class t a ?? +105 c conforming to jesd78a ii level a docid025451 rev 2 79/123 stm32f071xx electrical characteristics 99 functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode. while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (higher than 5 lsb tue), out of conventional limits of induced leakage current on adjacent pins (out of the -5 a/+0 a range) or other functional failure (for example reset occurrence or oscillator frequency deviation). the characterization results are given in table 53 . negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. 6.3.14 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 54 are derived from tests performed under the conditions summarized in table 24: general operating conditions . all i/os are designed as cmos- and ttl-compliant (except boot0). table 53. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 and pf1 pins ?0 na ma injected current on pc0 pin ?0 +5 injected current on pa11 and pa12 pins with induced leakage current on adjacent pins less than -1 ma ?5 na injected current on all other ft and ftf pins ?5 na injected current on all other tta, tc and rst pins ?5 +5 table 54. i/o static characteristics symbol parameter conditions min typ max unit v il low level input voltage tc and tta i/o - - 0.3 v ddiox +0.07 (1) v ft and ftf i/o - - 0.475 v ddiox ?0.2 (1) boot0 - - 0.3 v ddiox ?0.3 (1) all i/os except boot0 pin - - 0.3 v ddiox electrical characteristics stm32f071xx 80/123 docid025451 rev 2 v ih high level input voltage tc and tta i/o 0.445 v ddiox +0.398 (1) -- v ft and ftf i/o 0.5 v ddiox +0.2 (1) -- boot0 0.2 v ddiox +0.95 (1) -- all i/os except boot0 pin 0.7 v ddiox -- v hys schmitt trigger hysteresis tc and tta i/o - 200 (1) - mv ft and ftf i/o - 100 (1) - boot0 - 300 (1) - i lkg input leakage current (2) tc, ft and ftf i/o tta in digital mode v ss ? ? v in ? ?? v ddiox -- ? ? 0.1 a tta in digital mode v ddiox ? ? v in ? ?? v dda --1 tta in analog mode v ss ? ? v in ? ?? v dda -- ? ? 0.2 ft and ftf i/o (3) v ddiox ? ?? v in ? ?? 5 v --10 r pu weak pull-up equivalent resistor (4) v in ?? v ss 25 40 55 k ? r pd weak pull-down equivalent resistor (4) v in ?? v ddiox 25 40 55 k ? c io i/o pin capacitance - 5 - pf 1. data based on design simulation only. not tested in production. 2. the leakage could be higher than the maximum value, if negative current is injected on adjacent pins. refer to table 53: i/o current injection susceptibility . 3. to sustain a voltage higher than v ddiox +0.3 v, the internal pull-up/pull-down resistors must be disabled. 4. pull-up and pull-down resistors are designed with a true resistance in series with a switchable pmos/nmos. this pmos/nmos contribution to the series resistance is minimal (~10% order). table 54. i/o static characteristics (continued) symbol parameter conditions min typ max unit docid025451 rev 2 81/123 stm32f071xx electrical characteristics 99 all i/os are cmos- and ttl-compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements is shown in figure 20 for standard i/os, and in figure 21 for 5 v tolerant i/os. figure 21. tc and tta i/o input characteristics figure 22. five volt tolerant (ft and ftf) i/o input characteristics & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 ' ' , 2 [ 9 , + p l q 9 ' ' , 2 [ 7 h v w h g u d q j h 8 q g h i l q h g l q s x w u d q j h 9 , / p d [ 9 ' ' , 2 [ 9 , / p d [ 9 ' ' , 2 [ & 0 2 6 v w d q g d u g u h t x l u h p h q w v 7 h v w h g u d q j h 7 7 / v w d q g d u g u h t x l u h p h q w 7 7 / v w d q g d u g u h t x l u h p h q w 0 6 9 9 9 , 1 9 9 ' ' , 2 [ 0 6 9 7 7 / v w d q g d u g u h t x l u h p h q w 7 7 / v w d q g d u g u h t x l u h p h q w & 0 2 6 v w d q g d u g u h t x l u h p h q w v 7 h v w h g u d q j h 9 , + p l q 9 ' ' , 2 [ 9 , + p l q 9 ' ' , 2 [ 9 , / p d [ 9 ' ' , 2 [ 8 q g h i l q h g l q s x w u d q j h & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 ' ' , 2 [ 7 h v w h g u d q j h 9 9 , 1 9 9 ' ' , 2 [ electrical characteristics stm32f071xx 82/123 docid025451 rev 2 output driving current the gpios (general purpose input/outputs) can sink or source up to +/-8 ma, and sink or source up to +/- 20 ma (with a relaxed v ol /v oh ). in the user application, the number of i/o pins which can drive current must be limited to respect the absolute maximum rating specified in section 6.2 : ? the sum of the currents sourced by all the i/os on v ddiox, plus the maximum consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating ? i vdd (see table 21: voltage characteristics ). ? the sum of the currents sunk by all the i/os on v ss , plus the maximum consumption of the mcu sunk on v ss , cannot exceed the absolute maximum rating ? i vss (see table 21: voltage characteristics ). output voltage levels unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 24: general operating conditions . all i/os are cmos- and ttl-compliant (ft, tta or tc unless otherwise specified). table 55. output voltage characteristics (1) symbol parameter conditions min max unit v ol output low level voltage for an i/o pin cmos port (2) |i io | = 8 ma v ddiox ? 2.7 v - 0.4 v v oh output high level voltage for an i/o pin v ddiox ?0.4 - v ol output low level voltage for an i/o pin ttl port (2) |i io | = 8 ma v ddiox ? 2.7 v - 0.4 v v oh output high level voltage for an i/o pin 2.4 - v ol (3) output low level voltage for an i/o pin |i io | = 20 ma v ddiox ? 2.7 v - 1.3 v v oh (3) output high level voltage for an i/o pin v ddiox ?1.3 - v ol (3) output low level voltage for an i/o pin |i io | = 6 ma v ddiox ? 2 v - 0.4 v v oh (3) output high level voltage for an i/o pin v ddiox ?0.4 - v ol (3) output low level voltage for an i/o pin |i io | = 4 ma - 0.4 v v oh (3) output high level voltage for an i/o pin v ddiox ?0.4 - v v olfm+ (4) output low level voltage for an ftf i/o pin in fm+ mode |i io | = 20 ma v ddiox ? 2.7 v - 0.4 v |i io | = 10 ma - 0.4 v 1. the i io current sourced or sunk by the device must always respect the absolute maximum rating specified in table 21: voltage characteristics , and the sum of the currents sourced or sunk by all the i/os (i/o ports and control pins) must always respect the absolute maximum ratings ? i io . 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. 3. data based on characterization results. not tested in production. 4. data based on design simulation only. not tested in production. docid025451 rev 2 83/123 stm32f071xx electrical characteristics 99 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 23 and table 56 , respectively. unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 24: general operating conditions . table 56. i/o ac characteristics (1)(2) ospeedry [1:0] value (1) symbol parameter conditions min max unit x0 f max(io)out maximum frequency (3) c l = 50 pf, v ddiox ? 2 v - 2 mhz t f(io)out output fall time - 125 ns t r(io)out output rise time - 125 f max(io)out maximum frequency (3) c l = 50 pf, v ddiox ? 2 v - 1 mhz t f(io)out output fall time - 125 ns t r(io)out output rise time - 125 01 f max(io)out maximum frequency (3) c l = 50 pf, v ddiox ? 2 v - 10 mhz t f(io)out output fall time - 25 ns t r(io)out output rise time - 25 f max(io)out maximum frequency (3) c l = 50 pf, v ddiox ? 2 v - 4 mhz t f(io)out output fall time - 62.5 ns t r(io)out output rise time - 62.5 11 f max(io)out maximum frequency (3) c l = 30 pf, v ddiox ? 2.7 v - 50 mhz c l = 50 pf, v ddiox ? 2.7 v - 30 c l = 50 pf, 2 v ?? v ddiox ? 2.7 v - 20 c l = 50 pf, v ddiox ? 2 v - 10 t f(io)out output fall time c l = 30 pf, v ddiox ? 2.7 v - 5 ns c l = 50 pf, v ddiox ? 2.7 v - 8 c l = 50 pf, 2 v ?? v ddiox ? 2.7 v - 12 c l = 50 pf, v ddiox ? 2 v - 25 t r(io)out output rise time c l = 30 pf, v ddiox ? 2.7 v - 5 c l = 50 pf, v ddiox ? 2.7 v - 8 c l = 50 pf, 2 v ?? v ddiox ? 2.7 v - 12 c l = 50 pf, v ddiox ? 2 v - 25 electrical characteristics stm32f071xx 84/123 docid025451 rev 2 figure 23. i/o ac characteristics definition 6.3.15 nrst pin characteristics the nrst pin input driver uses the cmos technology. it is connected to a permanent pull- up resistor, r pu . unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 24: general operating conditions . fm+ configuration (4) f max(io)out maximum frequency (3) c l = 50 pf, v ddiox ? 2 v - 2 mhz t f(io)out output fall time - 12 ns t r(io)out output rise time - 34 f max(io)out maximum frequency (3) c l = 50 pf, v ddiox ? 2 v - 0.5 mhz t f(io)out output fall time - 16 ns t r(io)out output rise time - 44 t extipw pulse width of external signals detected by the exti controller 10 - ns 1. the i/o speed is configured using the ospeedrx[1:0] bits. refer to the stm32f0xxxx rm0091 reference manual for a description of gpio port configuration register. 2. guaranteed by design, not tested in production. 3. the maximum frequency is defined in figure 23 . 4. when fm+ configuration is set, the i/o speed control is bypassed. refer to the stm32f0xxxx reference manual rm0091 for a detailed description of fm+ i/o configuration. table 56. i/o ac characteristics (1)(2) (continued) ospeedry [1:0] value (1) symbol parameter conditions min max unit 0 6 9 7 0 d [ l p x p i u h t x h q f \ l v d f k l h y h g l i w w ? 7 d q g l i w k h g x w \ f \ f o h l v z k h q o r d g h g e \ w k h v s h f l i l h g f d s d f l w d q f h u i u , 2 r x w w i , 2 r x w w table 57. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) nrst input low level voltage - - 0.3 v dd +0.07 (1) v v ih(nrst) nrst input high level voltage 0.445 v dd +0.398 (1) -- docid025451 rev 2 85/123 stm32f071xx electrical characteristics 99 figure 24. recommended nrst pin protection 1. the reset network protects the device against parasitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 57: nrst pin characteristics . otherwise the reset will not be taken into account by the device. 6.3.16 12-bit adc characteristics unless otherwise specified, the parameters given in table 58 are preliminary values derived from tests performed under ambient temperature, f pclk frequency and v dda supply voltage conditions summarized in table 24: general operating conditions . note: it is recommended to perform a calibration after each power-up. v hys(nrst) nrst schmitt trigger voltage hysteresis - 200 - mv r pu weak pull-up equivalent resistor (2) v in ?? v ss 25 40 55 k ? v f(nrst) nrst input filtered pulse - - 100 (1) ns v nf(nrst) nrst input not filtered pulse 2.7 < v dd < 3.6 300 (1) -- ns 2.0 < v dd < 3.6 500 (1) -- 1. data based on design simulation only. not tested in production. 2. the pull-up is designed with a true resistance in series with a switchable pmos. this pmos contribution to the series resistance is minimal (~10% order) . table 57. nrst pin characteristics (continued) symbol parameter conditions min typ max unit 5 3 8 9 ' ' 0 6 9 , q w h u q d o u h v h w ( [ w h u q d o u h v h w f l u f x l w 1 5 6 7 ) l o w h u ? ) table 58. adc characteristics symbol parameter conditions min typ max unit v dda analog supply voltage for adc on 2.4 - 3.6 v i dda (adc) current consumption of the adc (1) v dd = v dda = 3.3 v - 0.9 - ma f adc adc clock frequency 0.6 - 14 mhz f s (2) sampling rate 0.05 - 1 mhz electrical characteristics stm32f071xx 86/123 docid025451 rev 2 equation 1: r ain max formula f trig (2) external trigger frequency f adc = 14 mhz - - 823 khz - - 17 1/f adc v ain conversion voltage range 0 - v dda v r ain (2) external input impedance see equation 1 and table 59 for details - - 50 k ? r adc (2) sampling switch resistance --1k ? c adc (2) internal sample and hold capacitor --8pf t cal (2) calibration time f adc = 14 mhz 5.9 s 83 1/f adc w latency (2) adc_dr register write latency adc clock = hsi14 1.5 adc cycles + 2 f pclk cycles - 1.5 adc cycles + 3 f pclk cycles adc clock = pclk/2 - 4.5 - f pclk cycle adc clock = pclk/4 - 8.5 - f pclk cycle t latr (2) trigger conversion latency f adc = f pclk /2 = 14 mhz 0.196 s f adc = f pclk /2 5.5 1/f pclk f adc = f pclk /4 = 12 mhz 0.219 s f adc = f pclk /4 10.5 1/f pclk f adc = f hsi14 = 14 mhz 0.188 - 0.259 s jitter adc adc jitter on trigger conversion f adc = f hsi14 -1-1/f hsi14 t s (2) sampling time f adc = 14 mhz 0.107 - 17.1 s 1.5 - 239.5 1/f adc t stab (2) power-up time 0 0 1 s t conv (2) total conversion time (including sampling time) f adc = 14 mhz 1 - 18 s 14 to 252 (t s for sampling +12.5 for successive approximation) 1/f adc 1. during conversion of the sampled value (12.5 x adc clock period), an additional consumption of 100 a on i dda and 60 a on i dd should be taken into account. 2. guaranteed by design, not tested in production. table 58. adc characteristics (continued) symbol parameter conditions min typ max unit r ain t s f adc c adc 2 n2 + ?? ln ? ? ------------------------------------------------------------- - r adc ? ? docid025451 rev 2 87/123 stm32f071xx electrical characteristics 99 the formula above ( equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of lsb. here n = 12 (from 12-bit resolution). table 59. r ain max for f adc = 14 mhz t s (cycles) t s ( s) r ain max (k ? ) (1) 1. guaranteed by design, not tested in production. 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 na 239.5 17.1 na table 60. adc accuracy (1)(2)(3) 1. adc dc accuracy values are measured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negative current on any of the standard (non- robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. any positive injection current within the limits specified for i inj(pin) and ? i inj(pin) in section 6.3.14 does not affect the adc accuracy. 3. better performance may be achieved in restricted v dda , frequency and temperature ranges. symbol parameter test conditions typ max (4) 4. data based on characterization results, not tested in production. unit et total unadjusted error f pclk = 48 mhz, f adc = 14 mhz, r ain < 10 k ? v dda = 3 v to 3.6 v t a = 25 c 1.3 2 lsb eo offset error 1 1.5 eg gain error 0.5 1.5 ed differential linearity error 0.7 1 el integral linearity error 0.8 1.5 et total unadjusted error f pclk = 48 mhz, f adc = 14 mhz, r ain < 10 k ? v dda = 2.7 v to 3.6 v t a = ? 40 to 105 c 3.3 4 lsb eo offset error 1.9 2.8 eg gain error 2.8 3 ed differential linearity error 0.7 1.3 el integral linearity error 1.2 1.7 et total unadjusted error f pclk = 48 mhz, f adc = 14 mhz, r ain < 10 k ? v dda = 2.4 v to 3.6 v t a = 25 c 3.3 4 lsb eo offset error 1.9 2.8 eg gain error 2.8 3 ed differential linearity error 0.7 1.3 el integral linearity error 1.2 1.7 electrical characteristics stm32f071xx 88/123 docid025451 rev 2 figure 25. adc accuracy characteristics figure 26. typical connection diagram using the adc 1. refer to table 58: adc characteristics for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. general pcb design guidelines power supply decoupling should be performed as shown in figure 12: power supply scheme . the 10 nf capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. ( 2 ( * / 6 % , ' ( $ / ( [ d p s o h r i d q d f w x d o w u d q v i h u f x u y h 7 k h l g h d o w u d q v i h u f x u y h ( q g s r l q w f r u u h o d w l r q o l q h ( 7 7 r w d o 8 q d g m x v w h g ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q w k h d f w x d o d q g w k h l g h d o w u d q v i h u f x u y h v ( 2 2 i i v h w ( u u r u g h y l d w l r q e h w z h h q w k h i l u v w d f w x d o w u d q v l w l r q d q g w k h i l u v w l g h d o r q h ( * * d l q ( u u r u g h y l d w l r q e h w z h h q w k h o d v w l g h d o w u d q v l w l r q d q g w k h o d v w d f w x d o r q h ( ' ' l i i h u h q w l d o / l q h d u l w \ ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q d f w x d o v w h s v d q g w k h l g h d o r q h ( / , q w h j u d o / l q h d u l w \ ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q d q \ d f w x d o w u d q v l w l r q d q g w k h h q g s r l q w f r u u h o d w l r q o l q h ( 7 ( ' ( / 9 ' ' $ 9 6 6 $ - 3 6 0 6 9 9 ' ' $ $ , 1 [ , / ? ? $ 9 7 5 $ , 1 & s d u d v l w l f 9 $ , 1 9 7 5 $ ' & e l w f r q y h u w h u & $ ' & 6 d p s o h d q g k r o g $ ' & f r q y h u w h u docid025451 rev 2 89/123 stm32f071xx electrical characteristics 99 6.3.17 dac electrical specifications table 61. dac characteristics symbol parameter min typ max unit comments v dda analog supply voltage for dac on 2.4 - 3.6 v r load (1) resistive load with buffer on 5- - k ? load is referred to ground r o (1) impedance output with buffer off - - 15 k ? when the buffer is off, the minimum resistive load between dac_out and v ss to have a 1% accuracy is 1.5 m ? c load (1) capacitive load - - 50 pf maximum capacitive load at dac_out pin (when the buffer is on). dac_out min (1) lower dac_out voltage with buffer on 0.2 - - v it gives the maximum output excursion of the dac. it corresponds to 12-bit input code (0x0e0) to (0xf1c) at v dda = 3.6 v and (0x155) and (0xeab) at v dda = 2.4 v dac_out max (1) higher dac_out voltage with buffer on --v dda ? 0.2 v dac_out min (1) lower dac_out voltage with buffer off - 0.5 - mv it gives the maximum output excursion of the dac. dac_out max (1) higher dac_out voltage with buffer off --v dda ? 1lsb v i dda dac dc current consumption in quiescent mode (2) - - 380 a with no load, middle code (0x800) on the input - - 480 a with no load, worst code (0xf1c) on the input dnl (3) differential non linearity difference between two consecutive code-1lsb) - - 0.5 lsb given for the dac in 10-bit configuration - - 2 lsb given for the dac in 12-bit configuration inl (3) integral non linearity (difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 1023) - - 1 lsb given for the dac in 10-bit configuration - - 4 lsb given for the dac in 12-bit configuration offset (3) offset error (difference between measured value at code (0x800) and the ideal value = v dda /2) - - 10 mv - - 3 lsb given for the dac in 10-bit at v dda = 3.6 v - - 12 lsb given for the dac in 12-bit at v dda = 3.6 v gain error (3) gain error - - 0.5 % given for the dac in 12-bit configuration electrical characteristics stm32f071xx 90/123 docid025451 rev 2 figure 27. 12-bit buffered / non-buffered dac 1. the dac integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. t settling (3) settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when dac_out reaches final value 1lsb -3 4 sc load ? 50 pf, r load ? 5 k ? update rate (3) max frequency for a correct dac_out change when small variation in the input code (from code i to i+1lsb) - - 1 ms/s c load ? 50 pf, r load ? 5 k ? t wakeup (3) wakeup time from off state (setting the enx bit in the dac control register) - 6.5 10 s c load ? 50 pf, r load ? 5 k ? input code between lowest and highest possible ones. psrr+ (1) power supply rejection ratio (to v dda ) (static dc measurement - ?67 ?40 db no r load , c load = 50 pf 1. guaranteed by design, not tested in production. 2. the dac is in ?quiescent mode? when it keeps the value steady on the output so no dynamic consumption is involved. 3. data based on characterization results, not tested in production. table 61. dac characteristics (continued) symbol parameter min typ max unit comments r load c load buffered/non-bu ffered dac dacx_out buffer(1) 12-bit digital to analog converter ai17157 docid025451 rev 2 91/123 stm32f071xx electrical characteristics 99 6.3.18 comparator characteristics table 62. comparator characteristics symbol parameter conditions min (1) typ max (1) unit v dda analog supply voltage 2 - 3.6 v v in comparator input voltage range 0-v dda v sc v refint scaler offset voltage - 5 10 mv t s_sc v refint scaler startup time from power down - - 0.2 ms t start comparator startup time startup time to reach propagation delay specification --60 s t d propagation delay for 200 mv step with 100 mv overdrive ultra-low power mode - 2 4.5 s low power mode - 0.7 1.5 medium power mode - 0.3 0.6 high speed mode v dda ? 2.7 v - 50 100 ns ? v dda ? 2.7 v - 100 240 propagation delay for full range step with 100 mv overdrive ultra-low power mode - 2 7 s low power mode - 0.7 2.1 medium power mode - 0.3 1.2 high speed mode v dda ? 2.7 v - 90 180 ns ? v dda ? 2.7 v - 110 300 v offset comparator offset error - ? 4 ? 10 mv dv offset /dt offset error temperature coefficient -18 - v/c i dd(comp) comp current consumption ultra-low power mode - 1.2 1.5 a low power mode - 3 5 medium power mode - 10 15 high speed mode - 75 100 electrical characteristics stm32f071xx 92/123 docid025451 rev 2 6.3.19 temperature sensor characteristics 6.3.20 v bat monitoring characteristics v hys comparator hysteresis no hysteresis (compxhyst[1:0]=00) -0 - mv low hysteresis (compxhyst[1:0]=01) high speed mode 3 8 13 all other power modes 510 medium hysteresis (compxhyst[1:0]=10) high speed mode 7 15 26 all other power modes 919 high hysteresis (compxhyst[1:0]=11) high speed mode 18 31 49 all other power modes 19 40 1. data based on characterization results, not tested in production. table 62. comparator characteristics (continued) symbol parameter conditions min (1) typ max (1) unit table 63. ts characteristics symbol parameter min typ max unit t l (1) 1. guaranteed by design, not tested in production. v sense linearity with temperature - ? ? 1 ? ? 2c avg_slope (1) average slope 4.0 4.3 4.6 mv/c v 30 voltage at 30 c ( ?? 5 c) (2) 2. measured at v dda = 3.3 v ?? 10 mv. the v 30 adc conversion result is stored in the ts_cal1 byte ?? refer to table 3: temperature sensor calibration values . 1.34 1.43 1.52 v t start (1) startup time 4 - 10 s t s_temp (1) adc sampling time when reading the temperature 4- - s table 64. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -50-k ? q ratio on v bat measurement - 2 - er (1) 1. guaranteed by design, not tested in production. error on q ?1 - +1 % t s_vbat (1) adc sampling time when reading the v bat 4- - s docid025451 rev 2 93/123 stm32f071xx electrical characteristics 99 6.3.21 timer characteristics the parameters given in the following tables are guaranteed by design. refer to section 6.3.14: i/o port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output). table 65. timx (1) characteristics 1. timx is used as a general term to refer to the tim1, tim2, tim3, tim6, tim14, tim15, tim16 and tim17 timers. symbol parameter conditions min max unit t res(tim) timer resolution time 1- t timxclk f timxclk = 48 mhz 20.8 - ns f ext timer external clock frequency on ch1 to ch4 0 f timxclk /2 mhz f timxclk = 48 mhz 0 24 mhz res tim timer resolution timx (except tim2) -16 bit tim2 - 32 t counter 16-bit counter clock period 1 65536 t timxclk f timxclk = 48 mhz 0.0208 1365 s t max_count maximum possible count with 32-bit counter - 65536 65536 t timxclk f timxclk = 48 mhz - 89.48 s table 66. iwdg min/max timeout period at 40 khz (lsi) (1) 1. these timings are given for a 40 khz clock but the microcontroller?s internal rc frequency can vary from 30 to 60 khz. moreover, given an exact rc oscillator frequency, the exact timings still depend on the phasing of the apb interface clock versus the lsi clock so that there is always a full rc period of uncertainty. prescaler divider pr[2:0] bits min timeout rl[11:0]= 0x000 max timeout rl[11:0]= 0xfff unit /4 0 0.1 409.6 ms /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 6 or 7 6.4 26214.4 electrical characteristics stm32f071xx 94/123 docid025451 rev 2 6.3.22 communication interfaces i 2 c interface characteristics the i2c interface meets the timings requirements of the i 2 c-bus specification and user manual rev. 03 for: ? standard-mode (sm): with a bit rate up to 100 kbit/s ? fast-mode (fm): with a bit rate up to 400 kbit/s ? fast-mode plus (fm+): with a bit rate up to 1 mbit/s. the i2c timings requirements are guaranteed by design when the i2c peripheral is properly configured (refer to reference manual). the sda and scl i/o requirements are met with the following restrictions: the sda and scl i/o pins are not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v ddiox is disabled, but is still present. only ftf i/o pins support fm+ low level output current maximum requirement. refer to section 6.3.14: i/o port characteristics for the i2c i/os characteristics. all i2c sda and scl i/os embed an analog filter. refer to the table below for the analog filter characteristics: table 67. wwdg min/max timeout value at 48 mhz (pclk) prescaler wdgtb min timeout value max timeout value unit 1 0 0.0853 5.4613 ms 2 1 0.1706 10.9226 4 2 0.3413 21.8453 8 3 0.6826 43.6906 table 68. i2c analog filter characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter min max unit t af maximum pulse width of spikes that are suppressed by the analog filter 50 (2) 2. spikes with widths below t af(min) are filtered. 260 (3) 3. spikes with widths above t af(max) are not filtered ns docid025451 rev 2 95/123 stm32f071xx electrical characteristics 99 spi/i 2 s characteristics unless otherwise specified, the parameters given in table 69 for spi or in table 70 for i 2 s are derived from tests performed under the ambient temperature, f pclkx frequency and supply voltage conditions summarized in table 24: general operating conditions . refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi and ws, ck, sd for i 2 s). table 69. spi characteristics (1) symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode - 18 mhz slave mode - 18 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 15 pf - 6 ns t su(nss) nss setup time slave mode 4tpclk - ns t h(nss) nss hold time slave mode 2tpclk + 10 - t w(sckh) t w(sckl) sck high and low time master mode, f pclk = 36 mhz, presc = 4 tpclk/2 -2 tpclk/2 + 1 t su(mi) t su(si) data input setup time master mode 4 - slave mode 5 - t h(mi) data input hold time master mode 4 - t h(si) slave mode 5 - t a(so) (2) data output access time slave mode, f pclk = 20 mhz 0 3tpclk t dis(so) (3) data output disable time slave mode 0 18 t v(so) data output valid time slave mode (after enable edge) - 22.5 t v(mo) data output valid time master mode (after enable edge) - 6 t h(so) data output hold time slave mode (after enable edge) 11.5 - t h(mo) master mode (after enable edge) 2 - ducy(sck) spi slave input clock duty cycle slave mode 25 75 % 1. data based on characterization results, not tested in production. 2. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z electrical characteristics stm32f071xx 96/123 docid025451 rev 2 figure 28. spi timing diagram - slave mode and cpha = 0 figure 29. spi timing diagram - slave mode and cpha = 1 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . a i c 3 # + ) n p u t # 0 ( ! - / 3 ) ) . 0 5 4 - ) 3 / / 5 4 0 5 4 # 0 ( ! - 3 " / 5 4 - 3 " ) . " ) 4 / 5 4 , 3 " ) . , 3 " / 5 4 # 0 / , # 0 / , " ) 4 ) . . 3 3 i n p u t t 3 5 . 3 3 t c 3 # + t h . 3 3 t a 3 / t w 3 # + ( t w 3 # + , t v 3 / t h 3 / t r 3 # + t f 3 # + t d i s 3 / t s u 3 ) t h 3 ) a i 3 # + ) n p u t # 0 ( ! - / 3 ) ) . 0 5 4 - ) 3 / / 5 4 0 5 4 # 0 ( ! - 3 " / 5 4 - 3 " ) . " ) 4 / 5 4 , 3 " ) . , 3 " / 5 4 # 0 / , # 0 / , " ) 4 ) . t 3 5 . 3 3 t c 3 # + t h . 3 3 t a 3 / t w 3 # , ( t w 3 # , , t v 3 / t h 3 / t r 3 # , t f 3 # , t d i s 3 / t s u 3 ) t h 3 ) . 3 3 i n p u t docid025451 rev 2 97/123 stm32f071xx electrical characteristics 99 figure 30. spi timing diagram - master mode 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . a i 6 3 # + / u t p u t # 0 ( ! - / 3 ) / 5 4 0 5 4 - ) 3 / ) . 0 5 4 # 0 ( ! - 3 " ) . - 3 " / 5 4 " ) 4 ) . , 3 " / 5 4 , 3 " ) . # 0 / , # 0 / , " ) 4 / 5 4 . 3 3 i n p u t t c 3 # + t w 3 # + ( t w 3 # + , t r 3 # + t f 3 # + t h - ) ( i g h 3 # + / u t p u t # 0 ( ! # 0 ( ! # 0 / , # 0 / , t s u - ) t v - / t h - / table 70. i 2 s characteristics (1) symbol parameter conditions min max unit f ck 1/t c(ck) i 2 s clock frequency master mode (data: 16 bits, audio frequency = 48 khz) 1.597 1.601 mhz slave mode 0 6.5 t r(ck) i 2 s clock rise time capacitive load c l = 15 pf - 10 ns t f(ck) i 2 s clock fall time - 12 t w(ckh) i2s clock high time master f pclk = 16 mhz, audio frequency = 48 khz 306 - t w(ckl) i2s clock low time 312 - t v(ws) ws valid time master mode 2 - t h(ws) ws hold time master mode 2 - t su(ws) ws setup time slave mode 7 - t h(ws) ws hold time slave mode 0 - ducy(sck) i2s slave input clock duty cycle slave mode 25 75 % electrical characteristics stm32f071xx 98/123 docid025451 rev 2 figure 31. i2s slave timing diagram (philips protocol) 1. measurement points are done at cmos levels: 0.3 v ddiox and 0.7 v ddiox . 2. lsb transmit/receive of the previously transmitted byte. no lsb transmit/receive is sent before the first byte. t su(sd_mr) data input setup time master receiver 6 - ns t su(sd_sr) data input setup time slave receiver 2 - t h(sd_mr) (2) data input hold time master receiver 4 - t h(sd_sr) (2) slave receiver 0.5 - t v(sd_st) (2) data output valid time slave transmitter (after enable edge) slave transmitter (after enable edge) master transmitter (after enable edge) master transmitter (after enable edge) -20 t h(sd_st) data output hold time 13 - t v(sd_mt) (2) data output valid time - 4 t h(sd_mt) data output hold time 0 - 1. data based on design simulation and/or characterization results, not tested in production. 2. depends on f pclk . for example, if f pclk = 8 mhz, then t pclk = 1/f plclk = 125 ns. table 70. i 2 s characteristics (1) (continued) symbol parameter conditions min max unit # + ) n p u t # 0 / , # 0 / , t c # + 7 3 i n p u t 3 $ t r a n s m i t 3 $ r e c e i v e t w # + ( t w # + , t s u 7 3 t v 3 $ ? 3 4 t h 3 $ ? 3 4 t h 7 3 t s u 3 $ ? 3 2 t h 3 $ ? 3 2 - 3 " r e c e i v e " i t n r e c e i v e , 3 " r e c e i v e - 3 " t r a n s m i t " i t n t r a n s m i t , 3 " t r a n s m i t a i b , 3 " r e c e i v e , 3 " t r a n s m i t docid025451 rev 2 99/123 stm32f071xx electrical characteristics 99 figure 32. i2s master timing diagram (philips protocol) 1. data based on characterization results, not tested in production. 2. lsb transmit/receive of the previously transmitted byte. no lsb transmit/receive is sent before the first byte. # + o u t p u t # 0 / , # 0 / , t c # + 7 3 o u t p u t 3 $ r e c e i v e 3 $ t r a n s m i t t w # + ( t w # + , t s u 3 $ ? - 2 t v 3 $ ? - 4 t h 3 $ ? - 4 t h 7 3 t h 3 $ ? - 2 - 3 " r e c e i v e " i t n r e c e i v e , 3 " r e c e i v e - 3 " t r a n s m i t " i t n t r a n s m i t , 3 " t r a n s m i t a i b t f # + t r # + t v 7 3 , 3 " r e c e i v e , 3 " t r a n s m i t package characteristics stm32f071xx 100/123 docid025451 rev 2 7 package characteristics 7.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. docid025451 rev 2 101/123 stm32f071xx package characteristics 121 figure 33. ufbga100 ? ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch, package outline 1. drawing is not to scale. a1 ball pad corner top view side view bottom view a1 ball pad corner e d e1 e fe d1 fd 0.50 0.10 a1 a a2 1.75 1.75 0.10 z x y a0c2_me b table 71. ufbga100 ? ultra fine pitch ball grid array, 7 x 7 mm, 0.50 mm pitch, package mechanical data symbol millimeters inches (1) min typ max min typ max a 0.460 0.530 0.600 0.0181 0.0209 0.0236 a1 0.060 0.080 0.100 0.0024 0.0031 0.0039 a2 0.400 0.450 0.500 0.0157 0.0177 0.0197 b 0.200 0.250 0.300 0.0079 0.0098 0.0118 d - 7.000 - - 0.2756 - d1 - 5.500 - - 0.2165 - e - 7.000 - - 0.2756 - e1 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - fd - 0.750 - - 0.0295 - fe - 0.750 - - 0.0295 - 1. values in inches are converted from mm and rounded to 4 decimal digits. package characteristics stm32f071xx 102/123 docid025451 rev 2 figure 34. ufbga100 recommended footprint marking of engineering samples for ufbga100 the following figure shows the engineering sample marking for the ufbga100 package. only the information field containing the engineering sample marking is shown. figure 35. ufbga100 package top view 1. samples marked ?e? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by st in writing. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. 0 6 9 ' v p ' s d g table 72. ufbga100 recommended pcb design rules dimension recommended values pitch 0.50 mm dpad 0.27 mm dsm 0.35 mm typ (depending on the soldermask registration tolerance) solder paste 0.27 mm aperture diameter ( q j l q h h u l q j v d p s o h p d u n l q j 0 6 9 ( 6 docid025451 rev 2 103/123 stm32f071xx package characteristics 121 figure 36. lqfp100 ? 14 x 14 mm 100 pin low-profile quad flat package outline 1. drawing is not to scale. e ) $ % . 4 ) & ) # ! 4 ) / . 0 ) . ' ! 5 ' % 0 , ! . % m m 3 % ! 4 ) . ' 0 , ! . % $ $ $ % % % + c c c # # , ? - % ? 6 ! ! ! , , c b ! table 73. lqfp100 ? 14 x 14 mm low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 - 12.000 - - 0.4724 - e 15.800 16.000 16.200 0.6220 0.6299 0.6378 package characteristics stm32f071xx 104/123 docid025451 rev 2 figure 37. lqfp100 recommended footprint 1. dimensions are in millimeters. e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 k 0 3.5 7 0 3.5 7 1. values in inches are converted from mm and rounded to 4 decimal digits. table 73. lqfp100 ? 14 x 14 mm low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max 75 51 50 76 0.5 0.3 16.7 14.3 100 26 12.3 25 1.2 16.7 1 ai14906b docid025451 rev 2 105/123 stm32f071xx package characteristics 121 marking of engineering samples for lqfp100 the following figure shows the engineering sample marking for the lqfp100 package. only the information field containing the engineering sample marking is shown. figure 38. lqfp100 package top view 1. samples marked ?es? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by st in writing. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. . 4 7 ( q j l q h h u l q j v d p s o h p d u n l q j ( 6 package characteristics stm32f071xx 106/123 docid025451 rev 2 figure 39. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline 1. drawing is not to scale. ! ! ! 3 % ! 4 ) . ' 0 , ! . % c c c # b # c ! , , + ' ! 5 ' % 0 , ! . % m m ) $ % . 4 ) & ) # ! 4 ) / . 0 ) . $ $ $ e % % % 7 ? - % ? 6 table 74. lqfp64 ? 10 x 10 mm low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 - 0.0079 d 11.800 12.000 12.200 0.4646 0.4724 0.4803 d1 9.800 10.000 10.200 0.3858 0.3937 0.4016 d3 - 7.500 - - 0.2953 - docid025451 rev 2 107/123 stm32f071xx package characteristics 121 figure 40. lqfp64 recommended footprint 1. dimensions are in millimeters. e 11.800 12.000 12.200 0.4646 0.4724 0.4803 e1 9.800 10.000 10.200 0.3858 0.3937 0.4016 e3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 k 0 3.5 7 0 3.5 7 1. values in inches are converted from mm and rounded to 4 decimal digits. table 74. lqfp64 ? 10 x 10 mm low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max a i b package characteristics stm32f071xx 108/123 docid025451 rev 2 marking of engineering samples for lqfp64 the following figure shows the engineering sample marking for the lqfp64 package. only the information field containing the engineering sample marking is shown. figure 41. lqfp64 package top view 1. samples marked ?es? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by st in writing. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. ( q j l q h h u l q j v d p s o h p d u n l q j . 4 7 ( 6 docid025451 rev 2 109/123 stm32f071xx package characteristics 121 figure 42. lqfp48 ? 7 x 7 mm, 48 pin low-profile quad flat package outline 1. drawing is not to scale. " ? - % ? 6 0 ) . ) $ % . 4 ) & ) # ! 4 ) / . c c c # # $ m m ' ! 5 ' % 0 , ! . % b ! ! ! c ! , , $ $ % % % e 3 % ! 4 ) . ' 0 , ! . % + table 75. lqfp48 ? 7 x 7 mm low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 - 5.500 - - 0.2165 - e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 - 5.500 - - 0.2165 - package characteristics stm32f071xx 110/123 docid025451 rev 2 figure 43. lqfp48 recommended footprint 1. dimensions are in millimeters. e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 k 0 3.5 7 0 3.5 7 1. values in inches are converted from mm and rounded to 4 decimal digits. table 75. lqfp48 ? 7 x 7 mm low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max a i d docid025451 rev 2 111/123 stm32f071xx package characteristics 121 marking of engineering samples for lqfp48 the following figure shows the engineering sample marking for the lqfp48 package. only the information field containing the engineering sample marking is shown. figure 44. lqfp48 package top view 1. samples marked ?es? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by st in writing. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. 0 6 9 ( q j l q h h u l q j v d p s o h p d u n l q j ( 6 package characteristics stm32f071xx 112/123 docid025451 rev 2 figure 45. ufqfpn48 ? 7 x 7 mm, 0.5 mm pitch, package outline 1. drawing is not to scale. 2. all leads/pads should also be soldered to the pcb to improve the lead/pad solder joint life. 3. there is an exposed die pad on the underside of the ufqfpn package. it is recommended to connect and solder this back-side pad to pcb ground. $ % b 0 ( b 9 ' 3 l q l g h q w l i l h u o d v h u p d u n l q j d u h d ( ( ' < ' ( ( [ s r v h g s d g d u h d = ' h w d l o = 5 w \ s / & [ ? s l q f r u q h u $ 6 h d w l q j s o d q h $ e h g g g ' h w d l o < 7 docid025451 rev 2 113/123 stm32f071xx package characteristics 121 figure 46. ufqfpn48 recommended footprint 1. dimensions are in millimeters. table 76. ufqfpn48 ? 7 x 7 mm, 0.5 mm pitch, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 0.000 0.020 0.050 0.0000 0.0008 0.0020 d 6.900 7.000 7.100 0.2717 0.2756 0.2795 e 6.900 7.000 7.100 0.2717 0.2756 0.2795 d2 5.500 5.600 5.700 0.2165 0.2205 0.2244 e2 5.500 5.600 5.700 0.2165 0.2205 0.2244 l 0.300 0.400 0.500 0.0118 0.0157 0.0197 t - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - 2 2 2 2 2 2 package characteristics stm32f071xx 114/123 docid025451 rev 2 marking of engineering samples for ufqfpn48 the following figure shows the engineering sample marking for the ufqfpn48 package. only the information field containing the engineering sample marking is shown. figure 47. ufqfpn48 package top view 1. samples marked ?es? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by st in writing. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. ( 6 ( q j l q h h u l q j v d p s o h p d u n l q j 0 6 9 docid025451 rev 2 115/123 stm32f071xx package characteristics 121 figure 48. wlcsp49 ? 0.4 mm pitch, package outline 1. drawing is not to scale. 2. dimension is measured at the maximum bump diameter parallel to primary datum z $ r u l h q w d w l r q u h i h u h q f h : d i h u e d f n v l g h ( ' ' h w d l o $ u r w d w h g ? 6 h d w l q j s o d q h $ % x p s e 6 l g h y l h z $ $ ' h w d l o $ * $ h ) * h h $ e d o o o r f d w l r q h ( $ % x p s v l g h ) u r q w y l h z $ ; / b 0 ( b 9 = e e e d d d ; h h h = package characteristics stm32f071xx 116/123 docid025451 rev 2 figure 49. wlcsp49 recommended footprint table 77. wlcsp49 ? 0.4 mm pitch package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.525 0.555 0.585 0.0207 0.0219 0.0230 a1 - 0.175 - - 0.0069 - a2 - 0.380 - - 0.0150 - a3 - 0.025 - - 0.0010 - b 0.220 0.250 0.280 0.0087 0.0098 0.0110 d 3.242 3.277 3.312 0.1276 0.1290 0.1304 e 3.074 3.109 3.144 0.1210 0.1224 0.1238 e - 0.400 - - 0.0157 - e1 - 2.400 - - 0.0945 - e2 - 2.400 - - 0.0945 - f - 0.438 - - 0.0173 - g - 0.354 - - 0.0140 - n49 aaa - 0.100 - - 0.0039 - bbb - 0.100 - - 0.0039 - ccc - 0.100 - - 0.0039 - ddd - 0.050 - - 0.0020 - eee - 0.050 - - 0.0020 - 0 6 9 ' v p ' s d g docid025451 rev 2 117/123 stm32f071xx package characteristics 121 marking of engineering samples for wlcsp49 the following figure shows the engineering sample marking for the wlcsp49 package. only the information field containing the engineering sample marking is shown. figure 50. wlcsp49 package top view 1. samples marked ?e? are to be considered as ?engineering samples?: i.e. they are intended to be sent to customer for electrical compatibility evaluation and may be used to start customer qualification where specifically authorized by st in writing. in no event st will be liable for any customer usage in production. only if st has authorized in writing the customer qualification engineering samples can be used for reliability qualification trials. table 78. wlcsp49 recommended pcb design rules (0.4 mm pitch bga) dimension recommended values pitch 0.4 mm dpad 260 m max. (circular) 220 m recommended dsm 300 m min. (for 260 m diameter pad) pcb pad design non-solder mask defined via underbump allowed ( q j l q h h u l q j v d p s o h p d u n l q j ( 0 6 9 package characteristics stm32f071xx 118/123 docid025451 rev 2 7.2 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 24: general operating conditions . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ? ja ) where: ? t a max is the maximum temperature in c, ?? ja is the package junction-to- thermal resistance, in ? c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = ?? (v ol i ol ) + ?? ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 7.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org 7.2.2 selecting the product temperature range when ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in section 8: part numbering . each temperature range suffix corresponds to a specific guaranteed temperature at maximum dissipation and to a specific maximum junction temperature. table 79. package thermal characteristics symbol parameter value unit ? ja thermal resistance junction- ufbga100 - 7 7 mm 55 c/w thermal resistance junction- lqfp100 - 14 14 mm 42 thermal resistance junction- lqfp64 - 10 10 mm / 0.5 mm pitch 44 thermal resistance junction- lqfp48 - 7 7 mm 54 thermal resistance junction- ufqfpn48 - 7 7 mm 32 thermal resistance junction- wlcsp49 - 0.4 mm pitch 49 docid025451 rev 2 119/123 stm32f071xx package characteristics 121 as applications do not commonly use the stm32f071xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range is best suited to the application. the following examples show how to calculate the temperature range needed for a given application. example 1: high-performance application assuming the following application conditions: maximum temperature t amax = 82 c (measured according to jesd51-2), i ddmax = 50 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v and maximum 8 i/os used at the same time in output at low level with i ol = 20 ma, v ol = 1.3 v p intmax = 50 ma 3.5 v= 175 mw p iomax = 20 8 ma 0.4 v + 8 20 ma 1.3 v = 272 mw this gives: p intmax = 175 mw and p iomax = 272 mw: p dmax = 175 + 272 = 447 mw using the values obtained in table 79 t jmax is calculated as follows: ? for lqfp64, 45 c/w t jmax = 82 c + (45 c/w 447 mw) = 82 c + 20.115 c = 102.115 c this is within the range of the suffix 6 version parts (?40 < t j < 105 c). in this case, parts must be ordered at least with the temperature range suffix 6 (see section 8: part numbering ). note: with this given p dmax we can find the t amax allowed for a given device temperature range (order code suffix 6 or 7). suffix 6: t amax = t jmax - (45c/w 447 mw) = 105-20.115 = 84.885 c suffix 7: t amax = t jmax - (45c/w 447 mw) = 125-20.115 = 104.885 c example 2: high-temperature application using the same rules, it is possible to address applications that run at high temperatures with a low dissipation, as long as junction temperature t j remains within the specified range. assuming the following application conditions: maximum temperature t amax = 100 c (measured according to jesd51-2), i ddmax = 20 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 20 ma 3.5 v= 70 mw p iomax = 20 8 ma 0.4 v = 64 mw this gives: p intmax = 70 mw and p iomax = 64 mw: p dmax = 70 + 64 = 134 mw thus: p dmax = 134 mw using the values obtained in table 79 t jmax is calculated as follows: ? for lqfp64, 45 c/w t jmax = 100 c + (45 c/w 134 mw) = 100 c + 6.03 c = 106.03 c package characteristics stm32f071xx 120/123 docid025451 rev 2 this is above the range of the suffix 6 version parts (?40 < t j < 105 c). in this case, parts must be ordered at least with the temperature range suffix 7 (see section 8: part numbering ) unless we reduce the power dissipation in order to be able to use suffix 6 parts. refer to figure 51 to select the required temperature range (suffix 6 or 7) according to your temperature or power requirements. figure 51. lqfp64 p d max vs. t a 0 6 y 9 6 x i i l [ 6 x i i l [ 3 ' p : 7 $ ? & docid025451 rev 2 121/123 stm32f071xx part numbering 121 8 part numbering for a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest st sales office. table 80. ordering information scheme example : stm32 f 071 r b t 6 x device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose sub-family 071 = stm32f071xx pin count c = 48/49 pins r = 64 pins v = 100 pins code size 8 = 64 kbytes of flash memory b = 128 kbytes of flash memory package h = ufbga t = lqfp u = ufqfpn y = wlcsp temperature range 6 = ?40 to 85 c 7 = ?40 to 105 c options xxx = programmed parts tr = tape and reel revision history stm32f071xx 122/123 docid025451 rev 2 9 revision history table 81. document revision history date revision changes 13-jan-2014 1 initial draft 21-feb-2014 2 added part number stm32f071v8. changed status of document from ?preliminary data? to ?production data?. updated ?reset and power management? data in features . updated t s_vrefint in table 28: embedded internal reference voltage . updated v hseh and v hsel in table 38: high-speed external user clock characteristics . updated v lseh and v lsel in table 39: low-speed external user clock characteristics . updated t s_temp in table 63: ts characteristics . updated t s_vbat in table 64: vbat monitoring characteristics . updated i2c interface characteristics section. updated figure 35: ufbga100 package top view and figure 50: wlcsp49 package top view . modified value of t s_sc and removed row v bg in table 62: comparator characteristics . docid025451 rev 2 123/123 stm32f071xx 123 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. a ll st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industr y domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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